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| author | Siyuan Wang <wangsiyuanbuaa@gmail.com> | 2013-01-04 13:07:49 +0800 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-01-04 06:37:19 +0100 |
| commit | 3d4762d450f63c32038b4c9c422dc99c98fdee9a (patch) | |
| tree | 19d55091b25a10d5d3ada27bec0511e76bc0dd84 | |
| parent | 086842a13e50d2c870ddf749c036f8c321d2915f (diff) | |
| download | coreboot-3d4762d450f63c32038b4c9c422dc99c98fdee9a.tar.xz | |
Tyan s8226: change lapic of lapic_cluster 0 to 0x10
There are two CPUs on s8226 and each CPU has 8 cores.
CPU 0 takes lapic from 0x10 to 0x17 and CPU 1 takes from 0x20 to 0x27.
So the first core's lapic is 0x10 rather than 0x20.
Change-Id: I925114d44f2f4974eb62c3832d8c9139a2a06c96
Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/2099
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
| -rw-r--r-- | src/mainboard/tyan/s8226/devicetree.cb | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/mainboard/tyan/s8226/devicetree.cb b/src/mainboard/tyan/s8226/devicetree.cb index 4459019d5c..a057f027e7 100644 --- a/src/mainboard/tyan/s8226/devicetree.cb +++ b/src/mainboard/tyan/s8226/devicetree.cb @@ -19,8 +19,7 @@ chip northbridge/amd/agesa/family15/root_complex device lapic_cluster 0 on chip cpu/amd/agesa/family15 - device lapic 0x20 on end #f15 - #device lapic 0x10 on end #f10 + device lapic 0x10 on end end end device pci_domain 0 on |