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| author | Felix Held <felix-coreboot@felixheld.de> | 2020-07-30 16:13:35 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-07-31 21:05:34 +0000 |
| commit | 42d52947934f20e419e42958ffb4973727a12e9c (patch) | |
| tree | cad36c037fc7c9e3c07f68a7b32fbfb97a127221 | |
| parent | 7d6dae68708a6063565eff110f36b36a7e4fc545 (diff) | |
| download | coreboot-42d52947934f20e419e42958ffb4973727a12e9c.tar.xz | |
vc/amd/fsp/picasso: document DXIO lane number mapping
Haven't found the official documentation for the DXIO lane mapping on
Pollock, so I had to guess that from the working configurations used in
google/dalboz and amd/cereme.
Change-Id: I53aac0aeba8466ae456f0f935114b587b64eeeaa
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44063
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/vendorcode/amd/fsp/picasso/platform_descriptors.h | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/src/vendorcode/amd/fsp/picasso/platform_descriptors.h b/src/vendorcode/amd/fsp/picasso/platform_descriptors.h index 2faa0abe97..9c0e3e93ac 100644 --- a/src/vendorcode/amd/fsp/picasso/platform_descriptors.h +++ b/src/vendorcode/amd/fsp/picasso/platform_descriptors.h @@ -113,6 +113,32 @@ typedef struct __packed { * Picasso DXIO Descriptor: Used for assigning lanes to PCIe/SATA/XGBE engines, configure * bifurcation and other settings. Beware that the lane numbers in here are the logical and not * the physical lane numbers! + * + * Picasso DXIO lane mapping: + * + * physical | logical | protocol + * ---------|---------|----------- + * GFX[7:0] | [15:8] | PCIe + * GPP[3:0] | [7:4] | PCIe + * GPP[5:4] | [1:0] | PCIe, XGBE + * GPP[7:6] | [3:2] | PCIe, SATA + * + * Dali has less DXIO connectivity than Picasso: + * + * physical | logical | protocol + * ---------|---------|----------- + * GFX[3:0] | [11:8] | PCIe + * GPP[1:0] | [5:4] | PCIe + * GPP[5:4] | [1:0] | PCIe, XGBE + * GPP[7:6] | [3:2] | SATA + * + * Pollock has even less DXIO lanes and the mapping of GPP lane numbers to the logical lane + * numbers differs to Picasso/Dali: + * + * physical | logical | protocol + * ---------|---------|---------- + * GPP[1:0] | [1:0] | PCIe + * GPP[3:2] | [5:4] | PCIe */ typedef struct __packed { uint8_t engine_type; |