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| author | Rizwan Qureshi <rizwan.qureshi@intel.com> | 2019-04-10 16:58:07 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2019-04-15 05:58:05 +0000 |
| commit | 43bb6554a24e1dd9944a7d3f518e4374f9e0be79 (patch) | |
| tree | 1f4cd7ca445aad110fc98521fc689eb29dadb817 | |
| parent | 2efee9df8581a5b1898d58c6d8f7ba3552ce1ed0 (diff) | |
| download | coreboot-43bb6554a24e1dd9944a7d3f518e4374f9e0be79.tar.xz | |
mb/google/hatch: Update sleep signal assertion widths
Based on the power rail discharge times measured on hatch,
update the assertions widths that have to be programmed in SoC.
BUG=b:129328209
TEST=warm/cold reboot and S3 are working fine on hatch.
Change-Id: I3c6dce0a942e6dcd9e55ef5e58a7e9e8d2b0a1e3
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32266
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
| -rw-r--r-- | src/mainboard/google/hatch/variants/baseboard/devicetree.cb | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 7dd41a2a3a..e39f140588 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -47,6 +47,11 @@ chip soc/intel/cannonlake # Unlock GPIO pads register "PchUnlockGpioPads" = "1" + register "PchPmSlpS3MinAssert" = "2" # 50ms + register "PchPmSlpS4MinAssert" = "1" # 1s + register "PchPmSlpSusMinAssert" = "1" # 500ms + register "PchPmSlpAMinAssert" = "3" # 2s + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 0 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 1 register "usb2_ports[2]" = "USB2_PORT_SHORT(OC3)" # Type-A Port 0 |