diff options
| author | Ben Gardner <gardner.ben@gmail.com> | 2016-06-01 09:25:28 -0500 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-06-03 04:54:32 +0200 |
| commit | 44bb9bdec86d2f0118fc6c1e8d6d0443cf81d235 (patch) | |
| tree | 257df888a04b75024a912d04fe0a28bbdde2d41a | |
| parent | e3a692d7daf16d53764a4b0e30531491d4ae24bd (diff) | |
| download | coreboot-44bb9bdec86d2f0118fc6c1e8d6d0443cf81d235.tar.xz | |
intel/fsp_baytrail/i2c: mask i2c interrupts in i2c_init()
i2c_init() leaves the I2C device enabled. Combined with the default
interrupt mask (0x8ff) and the fact that the interrupt line is shared,
this leads to an interrupt storm in the OS until a proper I2C driver
is loaded.
This change clears the interrupt mask to prevent the interrupt storm.
Change-Id: I0424a00753d06e26639750f065a7a08a710bfaba
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: https://review.coreboot.org/15047
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
| -rw-r--r-- | src/soc/intel/fsp_baytrail/i2c.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/fsp_baytrail/i2c.c b/src/soc/intel/fsp_baytrail/i2c.c index eb83180dd9..4565ba4ced 100644 --- a/src/soc/intel/fsp_baytrail/i2c.c +++ b/src/soc/intel/fsp_baytrail/i2c.c @@ -141,6 +141,8 @@ int i2c_init(unsigned bus) /* For 400 kHz, the counter value is 0x7d */ write32(base_ptr + I2C_FS_SCL_HCNT, 0x7d); write32(base_ptr + I2C_FS_SCL_LCNT, 0x7d); + /* no interrupts in BIOS */ + write32(base_ptr + I2C_INTR_MASK, 0); /* Enable the I2C controller for operation */ write32(base_ptr + I2C_ENABLE, 0x1); |