diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-12-07 13:15:23 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-12-25 21:41:55 +0000 |
| commit | 47a80a045d2f21c6e6857a9380538c086b99c876 (patch) | |
| tree | 0331c79ed8e869a27907739a159dbd4476372120 | |
| parent | 5db1b15147ee1221cebd49455369713c0fd29b4a (diff) | |
| download | coreboot-47a80a045d2f21c6e6857a9380538c086b99c876.tar.xz | |
nb/intel/sandybridge: Move steppings to CPU header
The steppings correspond to the CPUID bits 3:0, so move them to the CPU
scope, and include the CPU header from files using the stepping macros.
Change-Id: Idf8fba4911f98953bb909777aea57295774d8400
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48409
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/cpu/intel/model_206ax/model_206ax.h | 24 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_common.c | 1 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_common.h | 12 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_native.c | 1 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/sandybridge.h | 12 |
5 files changed, 26 insertions, 24 deletions
diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h index b6e2d65e96..195ef15810 100644 --- a/src/cpu/intel/model_206ax/model_206ax.h +++ b/src/cpu/intel/model_206ax/model_206ax.h @@ -6,6 +6,30 @@ #include <arch/cpu.h> #include <stdint.h> +/* SandyBridge CPU stepping */ +#define SNB_STEP_D0 5 /* Also J0 */ +#define SNB_STEP_D1 6 +#define SNB_STEP_D2 7 /* Also J1/Q0 */ + +/* IvyBridge CPU stepping */ +#define IVB_STEP_A0 0 +#define IVB_STEP_B0 2 +#define IVB_STEP_C0 4 +#define IVB_STEP_K0 5 +#define IVB_STEP_D0 6 + +#define IS_SANDY_CPU(x) ((x & 0xffff0) == 0x206a0) +#define IS_SANDY_CPU_C(x) ((x & 0xf) == 4) +#define IS_SANDY_CPU_D0(x) ((x & 0xf) == 5) +#define IS_SANDY_CPU_D1(x) ((x & 0xf) == 6) +#define IS_SANDY_CPU_D2(x) ((x & 0xf) == 7) + +#define IS_IVY_CPU(x) ((x & 0xffff0) == 0x306a0) +#define IS_IVY_CPU_C(x) ((x & 0xf) == 4) +#define IS_IVY_CPU_K(x) ((x & 0xf) == 5) +#define IS_IVY_CPU_D(x) ((x & 0xf) == 6) +#define IS_IVY_CPU_E(x) ((x & 0xf) >= 8) + /* SandyBridge/IvyBridge bus clock is fixed at 100MHz */ #define SANDYBRIDGE_BCLK 100 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 0b8e5ef20f..3c60a9f5d0 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -3,6 +3,7 @@ #include <assert.h> #include <commonlib/helpers.h> #include <console/console.h> +#include <cpu/intel/model_206ax/model_206ax.h> #include <string.h> #include <arch/cpu.h> #include <device/mmio.h> diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 53d0cd94ef..449912352f 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -8,18 +8,6 @@ #define BASEFREQ 133 #define tDLLK 512 -#define IS_SANDY_CPU(x) ((x & 0xffff0) == 0x206a0) -#define IS_SANDY_CPU_C(x) ((x & 0xf) == 4) -#define IS_SANDY_CPU_D0(x) ((x & 0xf) == 5) -#define IS_SANDY_CPU_D1(x) ((x & 0xf) == 6) -#define IS_SANDY_CPU_D2(x) ((x & 0xf) == 7) - -#define IS_IVY_CPU(x) ((x & 0xffff0) == 0x306a0) -#define IS_IVY_CPU_C(x) ((x & 0xf) == 4) -#define IS_IVY_CPU_K(x) ((x & 0xf) == 5) -#define IS_IVY_CPU_D(x) ((x & 0xf) == 6) -#define IS_IVY_CPU_E(x) ((x & 0xf) >= 8) - #define NUM_CHANNELS 2 #define NUM_SLOTRANKS 4 #define NUM_SLOTS 2 diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index 0d581f5a57..9961e89069 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -3,6 +3,7 @@ #include <commonlib/clamp.h> #include <console/console.h> #include <console/usb.h> +#include <cpu/intel/model_206ax/model_206ax.h> #include <delay.h> #include <device/device.h> #include <device/pci_def.h> diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index e5f2132ab8..235ca0e194 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -8,18 +8,6 @@ #define BASE_REV_IVB 0x50 #define BASE_REV_MASK 0x50 -/* SandyBridge CPU stepping */ -#define SNB_STEP_D0 5 /* Also J0 */ -#define SNB_STEP_D1 6 -#define SNB_STEP_D2 7 /* Also J1/Q0 */ - -/* IvyBridge CPU stepping */ -#define IVB_STEP_A0 0 -#define IVB_STEP_B0 2 -#define IVB_STEP_C0 4 -#define IVB_STEP_K0 5 -#define IVB_STEP_D0 6 - #include "memmap.h" /* Everything below this line is ignored in the DSDT */ |