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authorSven Schnelle <svens@stackframe.org>2011-05-03 07:55:30 +0000
committerSven Schnelle <svens@stackframe.org>2011-05-03 07:55:30 +0000
commit49ae971333408f2a37b9fd6752f6cc9b8fb7f5b4 (patch)
tree09617ea794ff7aba31c850b6b7a670cdec1b6542
parent8eee19d0eafd3a34742df4d26c810424097211fe (diff)
downloadcoreboot-49ae971333408f2a37b9fd6752f6cc9b8fb7f5b4.tar.xz
i82801gx: enable SPI prefetching
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Sven Schnelle <svens@stackframe.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6553 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
-rw-r--r--src/southbridge/intel/i82801gx/Kconfig5
-rw-r--r--src/southbridge/intel/i82801gx/bootblock.c40
2 files changed, 45 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig
index f63c12faaf..a6bd2026d9 100644
--- a/src/southbridge/intel/i82801gx/Kconfig
+++ b/src/southbridge/intel/i82801gx/Kconfig
@@ -38,5 +38,10 @@ config USBDEBUG_DEFAULT_PORT
int
default 1
+config BOOTBLOCK_SOUTHBRIDGE_INIT
+ string
+ default "southbridge/intel/i82801gx/bootblock.c"
+ depends on SOUTHBRIDGE_INTEL_I82801GX
+
endif
diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c
new file mode 100644
index 0000000000..39b0bd4191
--- /dev/null
+++ b/src/southbridge/intel/i82801gx/bootblock.c
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+
+static void enable_spi_prefetch(void)
+{
+ u8 reg8;
+ device_t dev;
+
+ dev = PCI_DEV(0, 0x1f, 0);
+
+ reg8 = pci_read_config8(dev, 0xdc);
+ reg8 &= ~(3 << 2);
+ reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
+ pci_write_config8(dev, 0xdc, reg8);
+}
+
+static void bootblock_southbridge_init(void)
+{
+ enable_spi_prefetch();
+}
+