soc/intel/jasperlake: Remove Tiger Lake SoC code from Jasper Lake

This is a follow-up patch to initial copy patch for Jasper Lake SoC. Remove all Tiger Lake specfic code from Jasper Lake SoC code. BUG=b:150217037 Change-Id: I44dc6bf55ca18a3f0c350f5c3e9fae2996958648 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39824 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
author: Aamir Bohra <aamir.bohra@intel.com> 2020-03-25 13:20:34 +0530
committer: Subrata Banik <subrata.banik@intel.com> 2020-03-28 14:08:23 +0000
commit: 512b77abb582e6c2566d3873b273dd32731e7bae (patch)
tree: 8807f78791588d361bd1cef00e11f6619203c713
parent: dd7acaad27e4f99f025df7f06d71dbb49d0e399b (diff)
download: coreboot-512b77abb582e6c2566d3873b273dd32731e7bae.tar.xz
66 files changed, 939 insertions, 3250 deletions
diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig
index ed2fece152..01d7294743 100644
--- a/src/soc/intel/jasperlake/Kconfig
+++ b/src/soc/intel/jasperlake/Kconfig
@@ -1,22 +1,9 @@
-config SOC_INTEL_TIGERLAKE_BASE_COPY
-	bool
-
-config SOC_INTEL_TIGERLAKE_COPY
-	bool
-	select SOC_INTEL_TIGERLAKE_BASE_COPY
-	#TODO - Enable INTEL_CAR_NEM_ENHANCED
-	select INTEL_CAR_NEM
-	help
-	  Intel Tigerlake support
-
 config SOC_INTEL_JASPERLAKE_COPY
 	bool
-	select SOC_INTEL_TIGERLAKE_BASE_COPY
-	select INTEL_CAR_NEM
 	help
 	  Intel Jasperlake support
 
-if SOC_INTEL_TIGERLAKE_BASE_COPY
+if SOC_INTEL_JASPERLAKE_COPY
 
 config CPU_SPECIFIC_OPTIONS
 	def_bool y
@@ -36,6 +23,7 @@ config CPU_SPECIFIC_OPTIONS
 	select INTEL_DESCRIPTOR_MODE_CAPABLE
 	select HAVE_SMI_HANDLER
 	select IDT_IN_EVERY_STAGE
+	select INTEL_CAR_NEM #TODO - Enable INTEL_CAR_NEM_ENHANCED
 	select INTEL_GMA_ACPI
 	select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
 	select IOAPIC
@@ -84,13 +72,12 @@ config DCACHE_RAM_SIZE
 
 config DCACHE_BSP_STACK_SIZE
 	hex
-	default 0x40400 if SOC_INTEL_TIGERLAKE_COPY
-	default 0x30400 if SOC_INTEL_JASPERLAKE_COPY
+	default 0x30400
 	help
 	  The amount of anticipated stack usage in CAR by bootblock and
-	  other stages. In the case of FSP_USES_CB_STACK default value will be
-	  sum of FSP-M stack requirement (256KiB for TGL, 192KiB for JSL) and CB romstage
-	  stack requirement (~1KiB).
+	  other stages. In the case of FSP_USES_CB_STACK default value
+	  will be sum of FSP-M stack requirement(192 KiB) and CB romstage
+	  stack requirement(~1KiB).
 
 config FSP_TEMP_RAM_SIZE
 	hex
@@ -102,8 +89,7 @@ config FSP_TEMP_RAM_SIZE
 
 config IFD_CHIPSET
 	string
-	default "jsl" if SOC_INTEL_JASPERLAKE_COPY
-	default "tgl" if SOC_INTEL_TIGERLAKE_COPY
+	default "jsl"
 
 config IED_REGION_SIZE
 	hex
@@ -115,13 +101,11 @@ config HEAP_SIZE
 
 config MAX_ROOT_PORTS
 	int
-	default 8 if SOC_INTEL_JASPERLAKE_COPY
-	default 12 if SOC_INTEL_TIGERLAKE_COPY
+	default 8
 
 config MAX_PCIE_CLOCKS
 	int
-	default 7 if SOC_INTEL_TIGERLAKE_COPY
-	default 6 if SOC_INTEL_JASPERLAKE_COPY
+	default 6
 
 config SMM_TSEG_SIZE
 	hex
@@ -155,8 +139,7 @@ config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
 
 config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
 	int
-	default 3 if SOC_INTEL_JASPERLAKE_COPY
-	default 4 if SOC_INTEL_TIGERLAKE_COPY
+	default 3
 
 config SOC_INTEL_I2C_DEV_MAX
 	int
@@ -173,17 +156,14 @@ config CONSOLE_UART_BASE_ADDRESS
 
 # Clock divider parameters for 115200 baud rate
 # Baudrate = (UART source clcok * M) /(N *16)
-# TGL UART source clock: 120MHz
 # JSL UART source clock: 100MHz
 config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
 	hex
-	default 0x30 if SOC_INTEL_JASPERLAKE_COPY
-	default 0x25a if SOC_INTEL_TIGERLAKE_COPY
+	default 0x30
 
 config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
 	hex
-	default 0xc35 if SOC_INTEL_JASPERLAKE_COPY
-	default 0x7fff if SOC_INTEL_TIGERLAKE_COPY
+	default 0xc35
 
 config CHROMEOS
 	select CHROMEOS_RAMOOPS_DYNAMIC
@@ -205,17 +185,15 @@ config CBFS_SIZE
 
 config FSP_HEADER_PATH
 	string "Location of FSP headers"
-	default "src/vendorcode/intel/fsp/fsp2_0/jasperlake/" if SOC_INTEL_JASPERLAKE_COPY
-	default "src/vendorcode/intel/fsp/fsp2_0/tigerlake/" if SOC_INTEL_TIGERLAKE_COPY
+	default "src/vendorcode/intel/fsp/fsp2_0/jasperlake/"
 
 config FSP_FD_PATH
 	string
 	depends on FSP_USE_REPO
-	default "3rdparty/fsp/JasperLakeFspBinPkg/Fsp.fd" if SOC_INTEL_JASPERLAKE_COPY
-	default "3rdparty/fsp/TigerLakeFspBinPkg/Fsp.fd" if SOC_INTEL_TIGERLAKE_COPY
+	default "3rdparty/fsp/JasperLakeFspBinPkg/Fsp.fd"
 
-config SOC_INTEL_TIGERLAKE_COPY_DEBUG_CONSENT
-	int "Debug Consent for TGL"
+config SOC_INTEL_JASPERLAKE_COPY_DEBUG_CONSENT
+	int "Debug Consent for JSL"
 	# USB DBC is more common for developers so make this default to 3 if
 	# SOC_INTEL_DEBUG_CONSENT=y
 	default 3 if SOC_INTEL_DEBUG_CONSENT
diff --git a/src/soc/intel/jasperlake/Makefile.inc b/src/soc/intel/jasperlake/Makefile.inc
index b02dc10250..29db4f3d00 100644
--- a/src/soc/intel/jasperlake/Makefile.inc
+++ b/src/soc/intel/jasperlake/Makefile.inc
@@ -1,4 +1,4 @@
-ifeq ($(CONFIG_SOC_INTEL_TIGERLAKE_BASE_COPY),y)
+ifeq ($(CONFIG_SOC_INTEL_JASPERLAKE_COPY),y)
 
 subdirs-y += romstage
 subdirs-y += ../../../cpu/intel/microcode
@@ -20,15 +20,12 @@ bootblock-y += bootblock/cpu.c
 bootblock-y += bootblock/pch.c
 bootblock-y += bootblock/report_platform.c
 bootblock-y += espi.c
-bootblock-$(CONFIG_SOC_INTEL_TIGERLAKE_COPY) += gpio_tgl.c
-bootblock-$(CONFIG_SOC_INTEL_JASPERLAKE_COPY) += gpio_jsl.c
+bootblock-y += gpio.c
 bootblock-y += p2sb.c
 
 romstage-y += espi.c
-romstage-$(CONFIG_SOC_INTEL_TIGERLAKE_COPY) += meminit_tgl.c
-romstage-$(CONFIG_SOC_INTEL_JASPERLAKE_COPY) += meminit_jsl.c
-romstage-$(CONFIG_SOC_INTEL_TIGERLAKE_COPY) += gpio_tgl.c
-romstage-$(CONFIG_SOC_INTEL_JASPERLAKE_COPY) += gpio_jsl.c
+romstage-y += gpio.c
+romstage-y += meminit.c
 romstage-y += reset.c
 
 ramstage-y += acpi.c
@@ -37,10 +34,8 @@ ramstage-y += cpu.c
 ramstage-y += elog.c
 ramstage-y += espi.c
 ramstage-y += finalize.c
-ramstage-$(CONFIG_SOC_INTEL_TIGERLAKE_COPY) += fsp_params_tgl.c
-ramstage-$(CONFIG_SOC_INTEL_JASPERLAKE_COPY) += fsp_params_jsl.c
-ramstage-$(CONFIG_SOC_INTEL_TIGERLAKE_COPY) += gpio_tgl.c
-ramstage-$(CONFIG_SOC_INTEL_JASPERLAKE_COPY) += gpio_jsl.c
+ramstage-y += fsp_params.c
+ramstage-y += gpio.c
 ramstage-y += graphics.c
 ramstage-y += lockdown.c
 ramstage-y += p2sb.c
@@ -50,17 +45,16 @@ ramstage-y += smmrelocate.c
 ramstage-y += systemagent.c
 ramstage-y += sd.c
 
-smm-$(CONFIG_SOC_INTEL_TIGERLAKE_COPY) += gpio_tgl.c
-smm-$(CONFIG_SOC_INTEL_JASPERLAKE_COPY) += gpio_jsl.c
+smm-y += gpio.c
 smm-y += p2sb.c
 smm-y += pmc.c
 smm-y += pmutil.c
 smm-y += smihandler.c
 smm-y += uart.c
 
-verstage-$(CONFIG_SOC_INTEL_TIGERLAKE_COPY) += gpio_tgl.c
+verstage-y += gpio.c
 
-CPPFLAGS_common += -I$(src)/soc/intel/tigerlake
-CPPFLAGS_common += -I$(src)/soc/intel/tigerlake/include
+CPPFLAGS_common += -I$(src)/soc/intel/jasperlake
+CPPFLAGS_common += -I$(src)/soc/intel/jasperlake/include
 
 endif
diff --git a/src/soc/intel/jasperlake/acpi/pci_irqs.asl b/src/soc/intel/jasperlake/acpi/pci_irqs.asl
index 474a6d6c1e..086282e733 100644
--- a/src/soc/intel/jasperlake/acpi/pci_irqs.asl
+++ b/src/soc/intel/jasperlake/acpi/pci_irqs.asl
@@ -13,8 +13,129 @@
  * GNU General Public License for more details.
  */
 
-#if CONFIG(SOC_INTEL_TIGERLAKE_COPY)
-	#include "pci_irqs_tgl.asl"
-#else
-	#include "pci_irqs_jsl.asl"
-#endif
+#include <soc/irq.h>
+
+Name (PICP, Package () {
+	/* cAVS, SMBus, GbE, Northpeak */
+	Package(){0x001FFFFF, 3, 0, cAVS_INTA_IRQ },
+	Package(){0x001FFFFF, 4, 0, SMBUS_INTB_IRQ },
+	Package(){0x001FFFFF, 6, 0, GbE_INTC_IRQ },
+	Package(){0x001FFFFF, 7, 0, TRACE_HUB_INTD_IRQ },
+	/* SerialIo */
+	Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ },
+	Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ },
+	Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ },
+	Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ },
+	/* PCI Express Port 1-8 */
+	Package(){0x001CFFFF, 0, 0, PCIE_1_IRQ },
+	Package(){0x001CFFFF, 1, 0, PCIE_2_IRQ },
+	Package(){0x001CFFFF, 2, 0, PCIE_3_IRQ },
+	Package(){0x001CFFFF, 3, 0, PCIE_4_IRQ },
+	Package(){0x001CFFFF, 4, 0, PCIE_5_IRQ },
+	Package(){0x001CFFFF, 5, 0, PCIE_6_IRQ },
+	Package(){0x001CFFFF, 6, 0, PCIE_7_IRQ },
+	Package(){0x001CFFFF, 7, 0, PCIE_8_IRQ },
+	/* eMMC */
+	Package(){0x001AFFFF, 0, 0, eMMC_IRQ },
+	/* SerialIo */
+	Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ },
+	Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ },
+	Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ },
+	/* SATA controller */
+	Package(){0x0017FFFF, 0, 0, SATA_IRQ },
+	/* CSME (HECI, IDE-R, Keyboard and Text redirection */
+	Package(){0x0016FFFF, 0, 0, HECI_1_IRQ },
+	Package(){0x0016FFFF, 1, 0, HECI_2_IRQ },
+	Package(){0x0016FFFF, 2, 0, IDER_IRQ },
+	Package(){0x0016FFFF, 3, 0, KT_IRQ },
+	Package(){0x0016FFFF, 4, 0, HECI_3_IRQ },
+	Package(){0x0016FFFF, 5, 0, HECI_4_IRQ },
+	/* SerialIo */
+	Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ },
+	Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ },
+	Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ },
+	Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ },
+	/* D20: xHCI, OTG, SRAM, CNVi WiFi, SD */
+	Package(){0x0014FFFF, 0, 0, XHCI_IRQ },
+	Package(){0x0014FFFF, 1, 0, OTG_IRQ },
+	Package(){0x0014FFFF, 2, 0, PMC_SRAM_IRQ },
+	Package(){0x0014FFFF, 3, 0, CNViWIFI_IRQ },
+	Package(){0x0014FFFF, 5, 0, SD_IRQ },
+	/* SerialIo */
+	Package(){0x0012FFFF, 6, 0, LPSS_SPI2_IRQ },
+	/* SA IGFX Device */
+	Package(){0x0002FFFF, 0, 0, IGFX_IRQ },
+	/* SA Thermal Device */
+	Package(){0x0004FFFF, 0, 0, SA_THERMAL_IRQ },
+	/* SA IPU Device */
+	Package(){0x0005FFFF, 0, 0, IPU_IRQ },
+	/* SA GNA Device */
+	Package(){0x0008FFFF, 0, 0, GNA_IRQ },
+})
+
+Name (PICN, Package () {
+	/* D31: cAVS, SMBus, GbE, Northpeak */
+	Package () { 0x001FFFFF, 3, 0, 11 },
+	Package () { 0x001FFFFF, 4, 0, 10 },
+	Package () { 0x001FFFFF, 6, 0, 11 },
+	Package () { 0x001FFFFF, 7, 0, 11 },
+	/* D30: SerialIo */
+	Package () {0x001EFFFF, 0, 0, 11 },
+	Package () {0x001EFFFF, 1, 0, 10 },
+	Package () {0x001EFFFF, 2, 0, 11 },
+	Package () {0x001EFFFF, 3, 0, 11 },
+	/* D28: PCI Express Port 1-8 */
+	Package () { 0x001CFFFF, 0, 0, 11 },
+	Package () { 0x001CFFFF, 1, 0, 10 },
+	Package () { 0x001CFFFF, 2, 0, 11 },
+	Package () { 0x001CFFFF, 3, 0, 11 },
+	Package () { 0x001CFFFF, 4, 0, 11 },
+	Package () { 0x001CFFFF, 5, 0, 10 },
+	Package () { 0x001CFFFF, 6, 0, 11 },
+	Package () { 0x001CFFFF, 7, 0, 11 },
+	/* D26: eMMC */
+	Package(){0x001AFFFF, 0, 0, 11 },
+	/* D25: SerialIo */
+	Package () {0x0019FFFF, 0, 0, 11 },
+	Package () {0x0019FFFF, 1, 0, 10 },
+	Package () {0x0019FFFF, 2, 0, 11 },
+	/* D23: SATA controller */
+	Package () { 0x0017FFFF, 0, 0, 11 },
+	/* D22: CSME (HECI, IDE-R, KT redirection */
+	Package () { 0x0016FFFF, 0, 0, 11 },
+	Package () { 0x0016FFFF, 1, 0, 10 },
+	Package () { 0x0016FFFF, 2, 0, 11 },
+	Package () { 0x0016FFFF, 3, 0, 11 },
+	Package () { 0x0016FFFF, 4, 0, 11 },
+	Package () { 0x0016FFFF, 5, 0, 11 },
+	/* D21: SerialIo */
+	Package () {0x0015FFFF, 0, 0, 11 },
+	Package () {0x0015FFFF, 1, 0, 10 },
+	Package () {0x0015FFFF, 2, 0, 11 },
+	Package () {0x0015FFFF, 3, 0, 11 },
+	/* D20: xHCI, OTG, SRAM, CNVi WiFi, SD */
+	Package () { 0x0014FFFF, 0, 0, 11 },
+	Package () { 0x0014FFFF, 1, 0, 10 },
+	Package () { 0x0014FFFF, 2, 0, 11 },
+	Package () { 0x0014FFFF, 3, 0, 11 },
+	Package () { 0x0014FFFF, 5, 0, 11 },
+	/* D18: SerialIo */
+	Package () {0x0012FFFF, 6, 0, 11 },
+	/* SA IGFX Device */
+	Package () {0x0002FFFF, 0, 0, 11 },
+	/* SA Thermal Device */
+	Package () { 0x0004FFFF, 0, 0, 11 },
+	/* SA IPU Device */
+	Package () { 0x0005FFFF, 0, 0, 11 },
+	/* SA GNA Device */
+	Package () { 0x0008FFFF, 0, 0, 11 },
+})
+
+Method (_PRT)
+{
+	If (PICM) {
+		Return (^PICP)
+	} Else {
+		Return (^PICN)
+	}
+}
diff --git a/src/soc/intel/jasperlake/acpi/pci_irqs_jsl.asl b/src/soc/intel/jasperlake/acpi/pci_irqs_jsl.asl
deleted file mode 100644
index 086282e733..0000000000
--- a/src/soc/intel/jasperlake/acpi/pci_irqs_jsl.asl
+++ /dev/null
@@ -1,141 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <soc/irq.h>
-
-Name (PICP, Package () {
-	/* cAVS, SMBus, GbE, Northpeak */
-	Package(){0x001FFFFF, 3, 0, cAVS_INTA_IRQ },
-	Package(){0x001FFFFF, 4, 0, SMBUS_INTB_IRQ },
-	Package(){0x001FFFFF, 6, 0, GbE_INTC_IRQ },
-	Package(){0x001FFFFF, 7, 0, TRACE_HUB_INTD_IRQ },
-	/* SerialIo */
-	Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ },
-	Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ },
-	Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ },
-	Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ },
-	/* PCI Express Port 1-8 */
-	Package(){0x001CFFFF, 0, 0, PCIE_1_IRQ },
-	Package(){0x001CFFFF, 1, 0, PCIE_2_IRQ },
-	Package(){0x001CFFFF, 2, 0, PCIE_3_IRQ },
-	Package(){0x001CFFFF, 3, 0, PCIE_4_IRQ },
-	Package(){0x001CFFFF, 4, 0, PCIE_5_IRQ },
-	Package(){0x001CFFFF, 5, 0, PCIE_6_IRQ },
-	Package(){0x001CFFFF, 6, 0, PCIE_7_IRQ },
-	Package(){0x001CFFFF, 7, 0, PCIE_8_IRQ },
-	/* eMMC */
-	Package(){0x001AFFFF, 0, 0, eMMC_IRQ },
-	/* SerialIo */
-	Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ },
-	Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ },
-	Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ },
-	/* SATA controller */
-	Package(){0x0017FFFF, 0, 0, SATA_IRQ },
-	/* CSME (HECI, IDE-R, Keyboard and Text redirection */
-	Package(){0x0016FFFF, 0, 0, HECI_1_IRQ },
-	Package(){0x0016FFFF, 1, 0, HECI_2_IRQ },
-	Package(){0x0016FFFF, 2, 0, IDER_IRQ },
-	Package(){0x0016FFFF, 3, 0, KT_IRQ },
-	Package(){0x0016FFFF, 4, 0, HECI_3_IRQ },
-	Package(){0x0016FFFF, 5, 0, HECI_4_IRQ },
-	/* SerialIo */
-	Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ },
-	Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ },
-	Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ },
-	Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ },
-	/* D20: xHCI, OTG, SRAM, CNVi WiFi, SD */
-	Package(){0x0014FFFF, 0, 0, XHCI_IRQ },
-	Package(){0x0014FFFF, 1, 0, OTG_IRQ },
-	Package(){0x0014FFFF, 2, 0, PMC_SRAM_IRQ },
-	Package(){0x0014FFFF, 3, 0, CNViWIFI_IRQ },
-	Package(){0x0014FFFF, 5, 0, SD_IRQ },
-	/* SerialIo */
-	Package(){0x0012FFFF, 6, 0, LPSS_SPI2_IRQ },
-	/* SA IGFX Device */
-	Package(){0x0002FFFF, 0, 0, IGFX_IRQ },
-	/* SA Thermal Device */
-	Package(){0x0004FFFF, 0, 0, SA_THERMAL_IRQ },
-	/* SA IPU Device */
-	Package(){0x0005FFFF, 0, 0, IPU_IRQ },
-	/* SA GNA Device */
-	Package(){0x0008FFFF, 0, 0, GNA_IRQ },
-})
-
-Name (PICN, Package () {
-	/* D31: cAVS, SMBus, GbE, Northpeak */
-	Package () { 0x001FFFFF, 3, 0, 11 },
-	Package () { 0x001FFFFF, 4, 0, 10 },
-	Package () { 0x001FFFFF, 6, 0, 11 },
-	Package () { 0x001FFFFF, 7, 0, 11 },
-	/* D30: SerialIo */
-	Package () {0x001EFFFF, 0, 0, 11 },
-	Package () {0x001EFFFF, 1, 0, 10 },
-	Package () {0x001EFFFF, 2, 0, 11 },
-	Package () {0x001EFFFF, 3, 0, 11 },
-	/* D28: PCI Express Port 1-8 */
-	Package () { 0x001CFFFF, 0, 0, 11 },
-	Package () { 0x001CFFFF, 1, 0, 10 },
-	Package () { 0x001CFFFF, 2, 0, 11 },
-	Package () { 0x001CFFFF, 3, 0, 11 },
-	Package () { 0x001CFFFF, 4, 0, 11 },
-	Package () { 0x001CFFFF, 5, 0, 10 },
-	Package () { 0x001CFFFF, 6, 0, 11 },
-	Package () { 0x001CFFFF, 7, 0, 11 },
-	/* D26: eMMC */
-	Package(){0x001AFFFF, 0, 0, 11 },
-	/* D25: SerialIo */
-	Package () {0x0019FFFF, 0, 0, 11 },
-	Package () {0x0019FFFF, 1, 0, 10 },
-	Package () {0x0019FFFF, 2, 0, 11 },
-	/* D23: SATA controller */
-	Package () { 0x0017FFFF, 0, 0, 11 },
-	/* D22: CSME (HECI, IDE-R, KT redirection */
-	Package () { 0x0016FFFF, 0, 0, 11 },
-	Package () { 0x0016FFFF, 1, 0, 10 },
-	Package () { 0x0016FFFF, 2, 0, 11 },
-	Package () { 0x0016FFFF, 3, 0, 11 },
-	Package () { 0x0016FFFF, 4, 0, 11 },
-	Package () { 0x0016FFFF, 5, 0, 11 },
-	/* D21: SerialIo */
-	Package () {0x0015FFFF, 0, 0, 11 },
-	Package () {0x0015FFFF, 1, 0, 10 },
-	Package () {0x0015FFFF, 2, 0, 11 },
-	Package () {0x0015FFFF, 3, 0, 11 },
-	/* D20: xHCI, OTG, SRAM, CNVi WiFi, SD */
-	Package () { 0x0014FFFF, 0, 0, 11 },
-	Package () { 0x0014FFFF, 1, 0, 10 },
-	Package () { 0x0014FFFF, 2, 0, 11 },
-	Package () { 0x0014FFFF, 3, 0, 11 },
-	Package () { 0x0014FFFF, 5, 0, 11 },
-	/* D18: SerialIo */
-	Package () {0x0012FFFF, 6, 0, 11 },
-	/* SA IGFX Device */
-	Package () {0x0002FFFF, 0, 0, 11 },
-	/* SA Thermal Device */
-	Package () { 0x0004FFFF, 0, 0, 11 },
-	/* SA IPU Device */
-	Package () { 0x0005FFFF, 0, 0, 11 },
-	/* SA GNA Device */
-	Package () { 0x0008FFFF, 0, 0, 11 },
-})
-
-Method (_PRT)
-{
-	If (PICM) {
-		Return (^PICP)
-	} Else {
-		Return (^PICN)
-	}
-}
diff --git a/src/soc/intel/jasperlake/acpi/pci_irqs_tgl.asl b/src/soc/intel/jasperlake/acpi/pci_irqs_tgl.asl
deleted file mode 100644
index 7f632ba32e..0000000000
--- a/src/soc/intel/jasperlake/acpi/pci_irqs_tgl.asl
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <soc/irq.h>
-
-Name (PICP, Package () {
-	/* D31:HSA, SMBUS, TraceHUB */
-	Package(){0x001FFFFF, 3, 0, HDA_IRQ },
-	Package(){0x001FFFFF, 4, 0, SMBUS_IRQ },
-	Package(){0x001FFFFF, 7, 0, TRACEHUB_IRQ },
-	/* D30: UART0, UART1, SPI0, SPI1 */
-	Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ },
-	Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ },
-	Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ },
-	Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ },
-	/* D29: RP9 ~ RP12 */
-	Package(){0x001DFFFF, 0, 0, PCIE_9_IRQ },
-	Package(){0x001DFFFF, 1, 0, PCIE_10_IRQ },
-	Package(){0x001DFFFF, 2, 0, PCIE_11_IRQ },
-	Package(){0x001DFFFF, 3, 0, PCIE_12_IRQ },
-	/* D28: RP1 ~ RP8 */
-	Package(){0x001CFFFF, 0, 0, PCIE_1_IRQ },
-	Package(){0x001CFFFF, 1, 0, PCIE_2_IRQ },
-	Package(){0x001CFFFF, 2, 0, PCIE_3_IRQ },
-	Package(){0x001CFFFF, 3, 0, PCIE_4_IRQ },
-	Package(){0x001CFFFF, 4, 0, PCIE_5_IRQ },
-	Package(){0x001CFFFF, 5, 0, PCIE_6_IRQ },
-	Package(){0x001CFFFF, 6, 0, PCIE_7_IRQ },
-	Package(){0x001CFFFF, 7, 0, PCIE_8_IRQ },
-	/* D25: I2C4, I2C5, UART2 */
-	Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ },
-	Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ },
-	Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ },
-	/* D23: SATA */
-	Package(){0x0017FFFF, 0, 0, SATA_IRQ },
-	/* D22: CSME */
-	Package(){0x0016FFFF, 0, 0, HECI_1_IRQ },
-	Package(){0x0016FFFF, 1, 0, HECI_2_IRQ },
-	Package(){0x0016FFFF, 4, 0, HECI_3_IRQ },
-	Package(){0x0016FFFF, 5, 0, HECI_4_IRQ },
-	/* D21: I2C0 ~ I2C3 */
-	Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ },
-	Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ },
-	Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ },
-	Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ },
-	/* D20: xHCI, xDCI, SRAM, CNVI_WIFI */
-	Package(){0x0014FFFF, 0, 0, xHCI_IRQ },
-	Package(){0x0014FFFF, 1, 0, xDCI_IRQ },
-	Package(){0x0014FFFF, 3, 0, CNVI_WIFI_IRQ },
-	/* D19: SPI3 */
-	Package(){0x0013FFFF, 0, 0, LPSS_SPI3_IRQ },
-	/* D18: ISH, SPI2 */
-	Package(){0x0012FFFF, 0, 0, ISH_IRQ },
-	Package(){0x0012FFFF, 6, 0, LPSS_SPI2_IRQ },
-	/* D16: CNVI_BT, TCH0, TCH1 */
-	Package(){0x0010FFFF, 2, 0, CNVI_BT_IRQ },
-	Package(){0x0010FFFF, 6, 0, THC0_IRQ },
-	Package(){0x0010FFFF, 7, 0, THC1_IRQ },
-	/* D13: xHCI, xDCI */
-	Package(){0x000DFFFF, 0, 0, xHCI_IRQ },
-	Package(){0x000DFFFF, 1, 0, xDCI_IRQ },
-	/* D8: GNA */
-	Package(){0x0008FFFF, 0, 0, GNA_IRQ },
-	/* D7: TBT PCIe */
-	Package(){0x0007FFFF, 0, 0, TBT_PCIe0_IRQ },
-	Package(){0x0007FFFF, 1, 0, TBT_PCIe1_IRQ },
-	Package(){0x0007FFFF, 2, 0, TBT_PCIe2_IRQ },
-	Package(){0x0007FFFF, 3, 0, TBT_PCIe3_IRQ },
-	/* D6: PEG60 */
-	Package(){0x0006FFFF, 0, 0, PEG_IRQ },
-	/* D5: IPU Device */
-	Package(){0x0005FFFF, 0, 0, IPU_IRQ },
-	/* D4:  Thermal Device */
-	Package(){0x0004FFFF, 0, 0, THERMAL_IRQ },
-	/* D2: IGFX */
-	Package(){0x0002FFFF, 0, 0, IGFX_IRQ },
-})
-
-Name (PICN, Package () {
-	/* D31:HSA, SMBUS, TraceHUB*/
-	Package () { 0x001FFFFF, 3, 0, 11 },
-	Package () { 0x001FFFFF, 4, 0, 11 },
-	Package () { 0x001FFFFF, 7, 0, 11 },
-	/* D30: UART0, UART1, SPI0, SPI1 */
-	Package () { 0x001EFFFF, 0, 0, 11 },
-	Package () { 0x001EFFFF, 1, 0, 10 },
-	Package () { 0x001EFFFF, 2, 0, 11 },
-	Package () { 0x001EFFFF, 3, 0, 11 },
-	/* D29: RP9 ~ RP12 */
-	Package () { 0x001DFFFF, 0, 0, 11 },
-	Package () { 0x001DFFFF, 1, 0, 10 },
-	Package () { 0x001DFFFF, 2, 0, 11 },
-	Package () { 0x001DFFFF, 3, 0, 11 },
-	/* D28: RP1 ~ RP8 */
-	Package () { 0x001CFFFF, 0, 0, 11 },
-	Package () { 0x001CFFFF, 1, 0, 10 },
-	Package () { 0x001CFFFF, 2, 0, 11 },
-	Package () { 0x001CFFFF, 3, 0, 11 },
-	Package () { 0x001CFFFF, 4, 0, 11 },
-	Package () { 0x001CFFFF, 5, 0, 10 },
-	Package () { 0x001CFFFF, 6, 0, 11 },
-	Package () { 0x001CFFFF, 7, 0, 11 },
-	/* D25: I2C4, I2C5, UART2 */
-	Package(){0x0019FFFF, 0, 0, 11 },
-	Package(){0x0019FFFF, 1, 0, 10 },
-	Package(){0x0019FFFF, 2, 0, 11 },
-	/* D23: SATA */
-	Package () { 0x0017FFFF, 0, 0, 11 },
-	/* D22: CSME */
-	Package(){0x0016FFFF, 0, 0, 11 },
-	Package(){0x0016FFFF, 1, 0, 10 },
-	Package(){0x0016FFFF, 4, 0, 11 },
-	Package(){0x0016FFFF, 5, 0, 11 },
-	/* D21: I2C0 ~ I2C3 */
-	Package(){0x0015FFFF, 0, 0, 11 },
-	Package(){0x0015FFFF, 1, 0, 10 },
-	Package(){0x0015FFFF, 2, 0, 11 },
-	Package(){0x0015FFFF, 3, 0, 11 },
-	/* D19: SPI3 */
-	Package(){0x0013FFFF, 0, 0, 11 },
-	/* D18: ISH, SPI2 */
-	Package(){0x0012FFFF, 0, 0, 11 },
-	Package(){0x0012FFFF, 6, 0, 11 },,
-	/* D16: CNVI_BT, TCH0, TCH1 */
-	Package(){0x0010FFFF, 2, 0, 11 },
-	Package(){0x0010FFFF, 6, 0, 11 },
-	Package(){0x0010FFFF, 7, 0, 10 },
-	/* D13: xHCI, xDCI */
-	Package(){0x000DFFFF, 0, 0, 11 },
-	Package(){0x000DFFFF, 1, 0, 10 },
-	/* D8: GNA */
-	Package(){0x0008FFFF, 0, 0, 11 },
-	/* D7: TBT PCIe */
-	Package(){0x0007FFFF, 0, 0, 11 },
-	Package(){0x0007FFFF, 1, 0, 10 },
-	Package(){0x0007FFFF, 2, 0, 11 },
-	Package(){0x0007FFFF, 3, 0, 11 },
-	/* D6: PEG60 */
-	Package(){0x0006FFFF, 0, 0, 11 },
-	/* D5: IPU Device */
-	Package(){0x0005FFFF, 0, 0, 11 },
-	/* D4:  Thermal Device */
-	Package(){0x0004FFFF, 0, 0, 11 },
-	/* D2: IGFX */
-	Package(){0x0002FFFF, 0, 0, 11 },
-})
-
-Method (_PRT)
-{
-	If (PICM) {
-		Return (^PICP)
-	} Else {
-		Return (^PICN)
-	}
-}
diff --git a/src/soc/intel/jasperlake/acpi/pmc.asl b/src/soc/intel/jasperlake/acpi/pmc.asl
index 6dd2d35354..0e3e24d94e 100644
--- a/src/soc/intel/jasperlake/acpi/pmc.asl
+++ b/src/soc/intel/jasperlake/acpi/pmc.asl
@@ -19,7 +19,7 @@ Scope (\_SB.PCI0) {
 	Device (PMC)
 	{
 		Name (_HID, "INTC1026")
-		Name (_DDN, "Intel(R) Tiger Lake IPC Controller")
+		Name (_DDN, "Intel(R) Jasper Lake IPC Controller")
 		/*
 		 * PCH preserved 32 MB MMIO range from 0xFC800000 to 0xFE7FFFFF.
 		 * 64KB (0xFE000000 - 0xFE00FFFF) for PMC MBAR.
diff --git a/src/soc/intel/jasperlake/acpi/xhci.asl b/src/soc/intel/jasperlake/acpi/xhci.asl
index 9baf67ac5a..41be89ace1 100644
--- a/src/soc/intel/jasperlake/acpi/xhci.asl
+++ b/src/soc/intel/jasperlake/acpi/xhci.asl
@@ -12,8 +12,51 @@
  * GNU General Public License for more details.
  */
 
-#if CONFIG(SOC_INTEL_TIGERLAKE_COPY)
-	#include "xhci_tgl.asl"
-#else
-	#include "xhci_jsl.asl"
-#endif
+#include <soc/gpe.h>
+
+/* XHCI Controller 0:14.0 */
+
+Device (XHCI)
+{
+	Name (_ADR, 0x00140000)
+
+	Name (_PRW, Package () { GPE0_PME_B0, 3 })
+
+	Name (_S3D, 3)	/* D3 supported in S3 */
+	Name (_S0W, 3)	/* D3 can wake device in S0 */
+	Name (_S3W, 3)	/* D3 can wake system from S3 */
+
+	Method (_PS0, 0, Serialized)
+	{
+
+	}
+
+	Method (_PS3, 0, Serialized)
+	{
+
+	}
+
+	/* Root Hub for Jasperlake PCH */
+	Device (RHUB)
+	{
+		Name (_ADR, Zero)
+
+		/* USB2 */
+		Device (HS01) { Name (_ADR, 1) }
+		Device (HS02) { Name (_ADR, 2) }
+		Device (HS03) { Name (_ADR, 3) }
+		Device (HS04) { Name (_ADR, 4) }
+		Device (HS05) { Name (_ADR, 5) }
+		Device (HS06) { Name (_ADR, 6) }
+		Device (HS07) { Name (_ADR, 7) }
+		Device (HS08) { Name (_ADR, 8) }
+
+		/* USB3 */
+		Device (SS01) { Name (_ADR, 9) }
+		Device (SS02) { Name (_ADR, 10) }
+		Device (SS03) { Name (_ADR, 11) }
+		Device (SS04) { Name (_ADR, 12) }
+		Device (SS05) { Name (_ADR, 13) }
+		Device (SS06) { Name (_ADR, 14) }
+	}
+}
diff --git a/src/soc/intel/jasperlake/acpi/xhci_jsl.asl b/src/soc/intel/jasperlake/acpi/xhci_jsl.asl
deleted file mode 100644
index 41be89ace1..0000000000
--- a/src/soc/intel/jasperlake/acpi/xhci_jsl.asl
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <soc/gpe.h>
-
-/* XHCI Controller 0:14.0 */
-
-Device (XHCI)
-{
-	Name (_ADR, 0x00140000)
-
-	Name (_PRW, Package () { GPE0_PME_B0, 3 })
-
-	Name (_S3D, 3)	/* D3 supported in S3 */
-	Name (_S0W, 3)	/* D3 can wake device in S0 */
-	Name (_S3W, 3)	/* D3 can wake system from S3 */
-
-	Method (_PS0, 0, Serialized)
-	{
-
-	}
-
-	Method (_PS3, 0, Serialized)
-	{
-
-	}
-
-	/* Root Hub for Jasperlake PCH */
-	Device (RHUB)
-	{
-		Name (_ADR, Zero)
-
-		/* USB2 */
-		Device (HS01) { Name (_ADR, 1) }
-		Device (HS02) { Name (_ADR, 2) }
-		Device (HS03) { Name (_ADR, 3) }
-		Device (HS04) { Name (_ADR, 4) }
-		Device (HS05) { Name (_ADR, 5) }
-		Device (HS06) { Name (_ADR, 6) }
-		Device (HS07) { Name (_ADR, 7) }
-		Device (HS08) { Name (_ADR, 8) }
-
-		/* USB3 */
-		Device (SS01) { Name (_ADR, 9) }
-		Device (SS02) { Name (_ADR, 10) }
-		Device (SS03) { Name (_ADR, 11) }
-		Device (SS04) { Name (_ADR, 12) }
-		Device (SS05) { Name (_ADR, 13) }
-		Device (SS06) { Name (_ADR, 14) }
-	}
-}
diff --git a/src/soc/intel/jasperlake/acpi/xhci_tgl.asl b/src/soc/intel/jasperlake/acpi/xhci_tgl.asl
deleted file mode 100644
index b97f52052b..0000000000
--- a/src/soc/intel/jasperlake/acpi/xhci_tgl.asl
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <soc/gpe.h>
-
-/* XHCI Controller 0:14.0 */
-
-Device (XHCI)
-{
-	Name (_ADR, 0x00140000)
-
-	Name (_PRW, Package () { GPE0_PME_B0, 3 })
-
-	Name (_S3D, 3)	/* D3 supported in S3 */
-	Name (_S0W, 3)	/* D3 can wake device in S0 */
-	Name (_S3W, 3)	/* D3 can wake system from S3 */
-
-	Method (_PS0, 0, Serialized)
-	{
-
-	}
-
-	Method (_PS3, 0, Serialized)
-	{
-
-	}
-
-	/* Root Hub for Tigerlake-LP PCH */
-	Device (RHUB)
-	{
-		Name (_ADR, Zero)
-
-		/* USB2 */
-		Device (HS01) { Name (_ADR, 1) }
-		Device (HS02) { Name (_ADR, 2) }
-		Device (HS03) { Name (_ADR, 3) }
-		Device (HS04) { Name (_ADR, 4) }
-		Device (HS05) { Name (_ADR, 5) }
-		Device (HS06) { Name (_ADR, 6) }
-		Device (HS07) { Name (_ADR, 7) }
-		Device (HS08) { Name (_ADR, 8) }
-		Device (HS09) { Name (_ADR, 9) }
-		Device (HS10) { Name (_ADR, 10) }
-
-		/* USB3 */
-		Device (SS01) { Name (_ADR, 13) }
-		Device (SS02) { Name (_ADR, 14) }
-		Device (SS03) { Name (_ADR, 15) }
-		Device (SS04) { Name (_ADR, 16) }
-	}
-}
diff --git a/src/soc/intel/jasperlake/bootblock/cpu.c b/src/soc/intel/jasperlake/bootblock/cpu.c
index dddf24352d..561172b2ae 100644
--- a/src/soc/intel/jasperlake/bootblock/cpu.c
+++ b/src/soc/intel/jasperlake/bootblock/cpu.c
@@ -12,19 +12,13 @@
  * GNU General Public License for more details.
  */
 
-/*
- * This file is created based on Intel Tiger Lake Processor PCH Datasheet
- * Document number: 575857
- * Chapter number: 6
- */
-
 #include <intelblocks/fast_spi.h>
 #include <soc/bootblock.h>
 
 void bootblock_cpu_init(void)
 {
 	/*
-	 * Tigerlake platform doesn't support booting from any other media
+	 * Jasperlake platform doesn't support booting from any other media
 	 * (like eMMC on APL/GLK platform) than only booting from SPI device
 	 * and on IA platform SPI is memory mapped hence enabling temporarily
 	 * cacheing on memory-mapped spi boot media.
diff --git a/src/soc/intel/jasperlake/bootblock/pch.c b/src/soc/intel/jasperlake/bootblock/pch.c
index b0646018c6..c98fdc5fb6 100644
--- a/src/soc/intel/jasperlake/bootblock/pch.c
+++ b/src/soc/intel/jasperlake/bootblock/pch.c
@@ -12,12 +12,6 @@
  * GNU General Public License for more details.
  */
 
-/*
- * This file is created based on Intel Tiger Lake Processor PCH Datasheet
- * Document number: 575857
- * Chapter number: 2, 3, 4, 27, 28
- */
-
 #include <console/console.h>
 #include <console/post_codes.h>
 #include <device/mmio.h>
@@ -39,8 +33,8 @@
 #include <soc/pcr_ids.h>
 #include <soc/pm.h>
 
-#define PCR_PSF3_TO_SHDW_PMC_REG_BASE_TGP	0x1100
-#define PCR_PSF3_TO_SHDW_PMC_REG_BASE_JSP	0xA00
+#define PCR_PSF3_TO_SHDW_PMC_REG_BASE	0xA00
+
 #define PCR_PSFX_TO_SHDW_BAR0	0
 #define PCR_PSFX_TO_SHDW_BAR1	0x4
 #define PCR_PSFX_TO_SHDW_BAR2	0x8
@@ -60,20 +54,6 @@
 #define PCR_DMI_LPCIOD		0x2770
 #define PCR_DMI_LPCIOE		0x2774
 
-static uint32_t get_pmc_reg_base(void)
-{
-	uint8_t pch_series;
-
-	pch_series = get_pch_series();
-
-	if (pch_series == PCH_TGP)
-		return PCR_PSF3_TO_SHDW_PMC_REG_BASE_TGP;
-	else if (pch_series == PCH_JSP)
-		return PCR_PSF3_TO_SHDW_PMC_REG_BASE_JSP;
-	else
-		return 0;
-}
-
 static void soc_config_pwrmbase(void)
 {
 	uint32_t reg32;
@@ -116,11 +96,7 @@ void bootblock_pch_early_init(void)
 static void soc_config_acpibase(void)
 {
 	uint32_t pmc_reg_value;
-	uint32_t pmc_base_reg;
-
-	pmc_base_reg = get_pmc_reg_base();
-	if (!pmc_base_reg)
-		die_with_post_code(POST_HW_INIT_FAILURE, "Invalid PMC base address\n");
+	uint32_t pmc_base_reg = PCR_PSF3_TO_SHDW_PMC_REG_BASE;
 
 	pmc_reg_value = pcr_read32(PID_PSF3, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4);
 
diff --git a/src/soc/intel/jasperlake/bootblock/report_platform.c b/src/soc/intel/jasperlake/bootblock/report_platform.c
index d7b2e0db32..35f2d1aead 100644
--- a/src/soc/intel/jasperlake/bootblock/report_platform.c
+++ b/src/soc/intel/jasperlake/bootblock/report_platform.c
@@ -12,12 +12,6 @@
  * GNU General Public License for more details.
  */
 
-/*
- * This file is created based on Intel Tiger Lake Platform Stepping and IDs
- * Document number: 605534
- * Chapter number: 2, 4, 5, 6
- */
-
 #include <arch/cpu.h>
 #include <device/pci_ops.h>
 #include <console/console.h>
@@ -36,7 +30,6 @@ static struct {
 	u32 cpuid;
 	const char *name;
 } cpu_table[] = {
-	{ CPUID_TIGERLAKE_A0, "Tigerlake A0" },
 	{ CPUID_JASPERLAKE_A0, "Jasperlake A0" },
 };
 
@@ -44,75 +37,22 @@ static struct {
 	u16 mchid;
 	const char *name;
 } mch_table[] = {
-	{ PCI_DEVICE_ID_INTEL_TGL_ID_U, "Tigerlake-U-4-2" },
-	{ PCI_DEVICE_ID_INTEL_TGL_ID_U_1, "Tigerlake-U-4-3e" },
-	{ PCI_DEVICE_ID_INTEL_TGL_ID_U_2_2, "Tigerlake-U-2-2" },
-	{ PCI_DEVICE_ID_INTEL_TGL_ID_Y, "Tigerlake-Y-4-2" },
 	{ PCI_DEVICE_ID_INTEL_JSL_ID_1, "Jasperlake-1" },
-	{ PCI_DEVICE_ID_INTEL_JSL_EHL, "Jasperlake Elkhartlake" },
-	{ PCI_DEVICE_ID_INTEL_EHL_ID_1, "Elkhartlake-1" },
 };
 
 static struct {
 	u16 espiid;
 	const char *name;
 } pch_table[] = {
-	{ PCI_DEVICE_ID_INTEL_TGP_ESPI_0, "Tigerlake-Base SKU" },
-	{ PCI_DEVICE_ID_INTEL_TGP_SUPER_U_ESPI, "Tigerlake-U Super SKU" },
-	{ PCI_DEVICE_ID_INTEL_TGP_PREMIUM_U_ESPI, "Tigerlake-U Premium SKU" },
-	{ PCI_DEVICE_ID_INTEL_TGP_BASE_U_ESPI, "Tigerlake-U Base SKU" },
-	{ PCI_DEVICE_ID_INTEL_TGP_ESPI_1, "Tigerlake-Base SKU" },
-	{ PCI_DEVICE_ID_INTEL_TGP_ESPI_2, "Tigerlake-Base SKU" },
-	{ PCI_DEVICE_ID_INTEL_TGP_SUPER_Y_ESPI, "Tigerlake-Y Super SKU" },
-	{ PCI_DEVICE_ID_INTEL_TGP_PREMIUM_Y_ESPI, "Tigerlake-Y Premium SKU" },
-	{ PCI_DEVICE_ID_INTEL_TGP_ESPI_3, "Tigerlake-Base SKU" },
-	{ PCI_DEVICE_ID_INTEL_TGP_ESPI_4, "Tigerlake-Base SKU" },
-	{ PCI_DEVICE_ID_INTEL_TGP_ESPI_5, "Tigerlake-Base SKU" },
-	{ PCI_DEVICE_ID_INTEL_TGP_ESPI_6, "Tigerlake-Base SKU" },
-	{ PCI_DEVICE_ID_INTEL_TGP_ESPI_7, "Tigerlake-Base SKU" },
-	{ PCI_DEVICE_ID_INTEL_TGP_ESPI_8, "Tigerlake-Base SKU" },
-	{ PCI_DEVICE_ID_INTEL_TGP_ESPI_9, "Tigerlake-Base SKU" },
-	{ PCI_DEVICE_ID_INTEL_TGP_ESPI_10, "Tigerlake-Base SKU" },
-	{ PCI_DEVICE_ID_INTEL_TGP_ESPI_11, "Tigerlake-Base SKU" },
-	{ PCI_DEVICE_ID_INTEL_TGP_ESPI_12, "Tigerlake-Base SKU" },
-	{ PCI_DEVICE_ID_INTEL_TGP_ESPI_13, "Tigerlake-Base SKU" },
-	{ PCI_DEVICE_ID_INTEL_TGP_ESPI_14, "Tigerlake-Base SKU" },
-	{ PCI_DEVICE_ID_INTEL_TGP_ESPI_15, "Tigerlake-Base SKU" },
-	{ PCI_DEVICE_ID_INTEL_TGP_ESPI_16, "Tigerlake-Base SKU" },
-	{ PCI_DEVICE_ID_INTEL_TGP_ESPI_17, "Tigerlake-Base SKU" },
-	{ PCI_DEVICE_ID_INTEL_TGP_ESPI_18, "Tigerlake-Base SKU" },
-	{ PCI_DEVICE_ID_INTEL_TGP_ESPI_19, "Tigerlake-Base SKU" },
-	{ PCI_DEVICE_ID_INTEL_TGP_ESPI_20, "Tigerlake-Base SKU" },
-	{ PCI_DEVICE_ID_INTEL_TGP_ESPI_21, "Tigerlake-Base SKU" },
-	{ PCI_DEVICE_ID_INTEL_TGP_ESPI_22, "Tigerlake-Base SKU" },
-	{ PCI_DEVICE_ID_INTEL_TGP_ESPI_23, "Tigerlake-Base SKU" },
-	{ PCI_DEVICE_ID_INTEL_TGP_ESPI_24, "Tigerlake-Base SKU" },
-	{ PCI_DEVICE_ID_INTEL_TGP_ESPI_25, "Tigerlake-Base SKU" },
-	{ PCI_DEVICE_ID_INTEL_TGP_ESPI_26, "Tigerlake-Base SKU" },
 	{ PCI_DEVICE_ID_INTEL_JSP_SUPER_ESPI, "Jasperlake Super" },
-	{ PCI_DEVICE_ID_INTEL_MCC_ESPI_0, "Elkhartlake-0" },
-	{ PCI_DEVICE_ID_INTEL_MCC_ESPI_1, "Elkhartlake-1" },
-	{ PCI_DEVICE_ID_INTEL_MCC_BASE_ESPI, "Elkhartlake Base" },
-	{ PCI_DEVICE_ID_INTEL_MCC_PREMIUM_ESPI, "Elkhartlake Premium" },
-	{ PCI_DEVICE_ID_INTEL_MCC_SUPER_ESPI, "Elkhartlake Super" },
 };
 
 static struct {
 	u16 igdid;
 	const char *name;
 } igd_table[] = {
-	{ PCI_DEVICE_ID_INTEL_TGL_GT0, "Tigerlake U GT0" },
-	{ PCI_DEVICE_ID_INTEL_TGL_GT2_ULT, "Tigerlake U GT2" },
-	{ PCI_DEVICE_ID_INTEL_TGL_GT2_ULX, "Tigerlake Y GT2" },
-	{ PCI_DEVICE_ID_INTEL_TGL_GT3_ULT, "Tigerlake U GT3" },
 	{ PCI_DEVICE_ID_INTEL_JSL_GT1, "Jasperlake GT1" },
 	{ PCI_DEVICE_ID_INTEL_JSL_GT2, "Jasperlake GT2" },
-	{ PCI_DEVICE_ID_INTEL_EHL_GT1_1, "Elkhartlake GT1 1" },
-	{ PCI_DEVICE_ID_INTEL_EHL_GT2_1, "Elkhartlake GT2 1" },
-	{ PCI_DEVICE_ID_INTEL_EHL_GT1_2, "Elkhartlake GT1 2" },
-	{ PCI_DEVICE_ID_INTEL_EHL_GT2_2, "Elkhartlake GT2 2" },
-	{ PCI_DEVICE_ID_INTEL_EHL_GT1_3, "Elkhartlake GT1 3" },
-	{ PCI_DEVICE_ID_INTEL_EHL_GT2_3, "Elkhartlake GT2 3" },
 };
 
 static inline uint8_t get_dev_revision(pci_devfn_t dev)
diff --git a/src/soc/intel/jasperlake/chip.c b/src/soc/intel/jasperlake/chip.c
index 1c7078d6cf..b7ed9df3d8 100644
--- a/src/soc/intel/jasperlake/chip.c
+++ b/src/soc/intel/jasperlake/chip.c
@@ -176,8 +176,8 @@ static void soc_enable(struct device *dev)
 		dev->ops = &cpu_bus_ops;
 }
 
-struct chip_operations soc_intel_tigerlake_ops = {
-	CHIP_NAME("Intel Tigerlake")
+struct chip_operations soc_intel_jasperlake_ops = {
+	CHIP_NAME("Intel Jasperlake")
 	.enable_dev	= &soc_enable,
 	.init		= &soc_init_pre_device,
 };
diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h
index f82f13d45b..8611674332 100644
--- a/src/soc/intel/jasperlake/chip.h
+++ b/src/soc/intel/jasperlake/chip.h
@@ -33,7 +33,7 @@
 #define MAX_HD_AUDIO_SNDW_LINKS 4
 #define MAX_HD_AUDIO_SSP_LINKS  6
 
-struct soc_intel_tigerlake_config {
+struct soc_intel_jasperlake_config {
 
 	/* Common struct containing soc config data required by common code */
 	struct soc_intel_common_config common_soc_config;
@@ -294,6 +294,6 @@ struct soc_intel_tigerlake_config {
 
 };
 
-typedef struct soc_intel_tigerlake_config config_t;
+typedef struct soc_intel_jasperlake_config config_t;
 
 #endif
diff --git a/src/soc/intel/jasperlake/cpu.c b/src/soc/intel/jasperlake/cpu.c
index dfbcd22b94..57719c2d7b 100644
--- a/src/soc/intel/jasperlake/cpu.c
+++ b/src/soc/intel/jasperlake/cpu.c
@@ -12,12 +12,6 @@
  * GNU General Public License for more details.
  */
 
-/*
- * This file is created based on Intel Tiger Lake Processor CPU Datasheet
- * Document number: 575683
- * Chapter number: 15
- */
-
 #include <arch/cpu.h>
 #include <console/console.h>
 #include <device/pci.h>
diff --git a/src/soc/intel/jasperlake/espi.c b/src/soc/intel/jasperlake/espi.c
index da36ea6304..500644e104 100644
--- a/src/soc/intel/jasperlake/espi.c
+++ b/src/soc/intel/jasperlake/espi.c
@@ -12,12 +12,6 @@
  * GNU General Public License for more details.
  */
 
-/*
- * This file is created based on Intel Tiger Lake Processor PCH Datasheet
- * Document number: 575857
- * Chapter number: 2
- */
-
 #include <device/device.h>
 #include <device/pci.h>
 #include <pc80/isa-dma.h>
@@ -41,14 +35,14 @@
 * certain memory range as reserved range for BIOS usage.
 * For this SOC, the range will be from 0FC800000h till FE7FFFFFh"
 */
-static const struct lpc_mmio_range tgl_lpc_fixed_mmio_ranges[] = {
+static const struct lpc_mmio_range jsl_lpc_fixed_mmio_ranges[] = {
 	{ PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE },
 	{ 0, 0 }
 };
 
 const struct lpc_mmio_range *soc_get_fixed_mmio_ranges()
 {
-	return tgl_lpc_fixed_mmio_ranges;
+	return jsl_lpc_fixed_mmio_ranges;
 }
 
 void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec)
@@ -70,24 +64,6 @@ void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec)
 	pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]);
 }
 
-uint8_t get_pch_series(void)
-{
-	uint16_t lpc_did_hi_byte;
-
-	/*
-	 * Fetch upper 8 bits on ESPI device ID to determine PCH type
-	 * Adding 1 to the offset to fetch upper 8 bits
-	 */
-	lpc_did_hi_byte = pci_read_config8(PCH_DEV_ESPI, PCI_DEVICE_ID + 1);
-
-	if (lpc_did_hi_byte == 0xA0)
-		return PCH_TGP;
-	else if (lpc_did_hi_byte == 0x4d)
-		return PCH_JSP;
-	else
-		return PCH_UNKNOWN_SERIES;
-}
-
 #if ENV_RAMSTAGE
 static void soc_mirror_dmi_pcr_io_dec(void)
 {
diff --git a/src/soc/intel/jasperlake/finalize.c b/src/soc/intel/jasperlake/finalize.c
index b636ccbec0..714cda15e5 100644
--- a/src/soc/intel/jasperlake/finalize.c
+++ b/src/soc/intel/jasperlake/finalize.c
@@ -12,12 +12,6 @@
  * GNU General Public License for more details.
  */
 
-/*
- * This file is created based on Intel Tiger Lake Processor PCH Datasheet
- * Document number: 575857
- * Chapter number: 4, 29
- */
-
 #include <arch/io.h>
 #include <device/mmio.h>
 #include <bootstate.h>
diff --git a/src/soc/intel/jasperlake/fsp_params_jsl.c b/src/soc/intel/jasperlake/fsp_params.c
index 932bd06ff7..be73ab7319 100644
--- a/src/soc/intel/jasperlake/fsp_params_jsl.c
+++ b/src/soc/intel/jasperlake/fsp_params.c
@@ -42,7 +42,7 @@ static const pci_devfn_t serial_io_dev[] = {
 
 static void parse_devicetree(FSP_S_CONFIG *params)
 {
-	const struct soc_intel_tigerlake_config *config = config_of_soc();
+	const struct soc_intel_jasperlake_config *config = config_of_soc();
 
 	/* LPSS controllers configuration */
 
@@ -81,7 +81,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	unsigned int i;
 	struct device *dev;
 	FSP_S_CONFIG *params = &supd->FspsConfig;
-	struct soc_intel_tigerlake_config *config = config_of_soc();
+	struct soc_intel_jasperlake_config *config = config_of_soc();
 
 	/* Parse device tree and fill in FSP UPDs */
 	parse_devicetree(params);
diff --git a/src/soc/intel/jasperlake/fsp_params_tgl.c b/src/soc/intel/jasperlake/fsp_params_tgl.c
deleted file mode 100644
index a8be407d23..0000000000
--- a/src/soc/intel/jasperlake/fsp_params_tgl.c
+++ /dev/null
@@ -1,212 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <assert.h>
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <fsp/api.h>
-#include <fsp/util.h>
-#include <intelblocks/lpss.h>
-#include <intelblocks/xdci.h>
-#include <soc/gpio_soc_defs.h>
-#include <soc/intel/common/vbt.h>
-#include <soc/pci_devs.h>
-#include <soc/ramstage.h>
-#include <soc/soc_chip.h>
-#include <string.h>
-
-/*
- * Chip config parameter PcieRpL1Substates uses (UPD value + 1)
- * because UPD value of 0 for PcieRpL1Substates means disabled for FSP.
- * In order to ensure that mainboard setting does not disable L1 substates
- * incorrectly, chip config parameter values are offset by 1 with 0 meaning
- * use FSP UPD default. get_l1_substate_control() ensures that the right UPD
- * value is set in fsp_params.
- * 0: Use FSP UPD default
- * 1: Disable L1 substates
- * 2: Use L1.1
- * 3: Use L1.2 (FSP UPD default)
- */
-static int get_l1_substate_control(enum L1_substates_control ctl)
-{
-	if ((ctl > L1_SS_L1_2) || (ctl == L1_SS_FSP_DEFAULT))
-		ctl = L1_SS_L1_2;
-	return ctl - 1;
-}
-
-static void parse_devicetree(FSP_S_CONFIG *params)
-{
-	const struct soc_intel_tigerlake_config *config;
-	config = config_of_soc();
-
-	for (int i = 0; i < CONFIG_SOC_INTEL_I2C_DEV_MAX; i++)
-		params->SerialIoI2cMode[i] = config->SerialIoI2cMode[i];
-
-	for (int i = 0; i < CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX; i++) {
-		params->SerialIoSpiMode[i] = config->SerialIoGSpiMode[i];
-		params->SerialIoSpiCsMode[i] = config->SerialIoGSpiCsMode[i];
-		params->SerialIoSpiCsState[i] = config->SerialIoGSpiCsState[i];
-	}
-
-	for (int i = 0; i < CONFIG_SOC_INTEL_UART_DEV_MAX; i++)
-		params->SerialIoUartMode[i] = config->SerialIoUartMode[i];
-}
-
-static const pci_devfn_t serial_io_dev[] = {
-	PCH_DEVFN_I2C0,
-	PCH_DEVFN_I2C1,
-	PCH_DEVFN_I2C2,
-	PCH_DEVFN_I2C3,
-	PCH_DEVFN_I2C4,
-	PCH_DEVFN_I2C5,
-	PCH_DEVFN_GSPI0,
-	PCH_DEVFN_GSPI1,
-	PCH_DEVFN_GSPI2,
-	PCH_DEVFN_GSPI3,
-	PCH_DEVFN_UART0,
-	PCH_DEVFN_UART1,
-	PCH_DEVFN_UART2
-};
-
-/* UPD parameters to be initialized before SiliconInit */
-void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
-{
-	int i;
-	FSP_S_CONFIG *params = &supd->FspsConfig;
-
-	struct device *dev;
-	struct soc_intel_tigerlake_config *config;
-	config = config_of_soc();
-
-	/* Parse device tree and enable/disable Serial I/O devices */
-	parse_devicetree(params);
-
-	/* Load VBT before devicetree-specific config. */
-	params->GraphicsConfigPtr = (uintptr_t)vbt_get();
-
-	params->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT;
-
-	dev = pcidev_path_on_root(SA_DEVFN_IGD);
-	if (CONFIG(RUN_FSP_GOP) && dev && dev->enabled)
-		params->PeiGraphicsPeimInit = 1;
-	else
-		params->PeiGraphicsPeimInit = 0;
-
-	for (i = 0; i < 8; i++)
-		params->IomTypeCPortPadCfg[i] = 0x09000000;
-
-	/* USB */
-	for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
-		params->PortUsb20Enable[i] = config->usb2_ports[i].enable;
-		params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin;
-		params->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias;
-		params->Usb2PhyTxiset[i] = config->usb2_ports[i].tx_bias;
-		params->Usb2PhyPredeemp[i] = config->usb2_ports[i].tx_emp_enable;
-		params->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit;
-	}
-
-	for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) {
-		params->PortUsb30Enable[i] = config->usb3_ports[i].enable;
-		params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;
-		if (config->usb3_ports[i].tx_de_emp) {
-			params->Usb3HsioTxDeEmphEnable[i] = 1;
-			params->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp;
-		}
-		if (config->usb3_ports[i].tx_downscale_amp) {
-			params->Usb3HsioTxDownscaleAmpEnable[i] = 1;
-			params->Usb3HsioTxDownscaleAmp[i] =
-				config->usb3_ports[i].tx_downscale_amp;
-		}
-	}
-
-	/* RP Configs */
-	for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++)
-		params->PcieRpL1Substates[i] =
-			get_l1_substate_control(config->PcieRpL1Substates[i]);
-
-	/* Enable xDCI controller if enabled in devicetree and allowed */
-	dev = pcidev_on_root(PCH_DEV_SLOT_XHCI, 1);
-	if (dev) {
-		if (!xdci_can_enable())
-			dev->enabled = 0;
-		params->XdciEnable = dev->enabled;
-	} else {
-		params->XdciEnable = 0;
-	}
-
-	/* PCH UART selection for FSP Debug */
-	params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE;
-	ASSERT(ARRAY_SIZE(params->SerialIoUartAutoFlow) > CONFIG_UART_FOR_CONSOLE);
-	params->SerialIoUartAutoFlow[CONFIG_UART_FOR_CONSOLE] = 0;
-
-	/* SATA */
-	dev = pcidev_on_root(PCH_DEV_SLOT_SATA, 0);
-	if (!dev)
-		params->SataEnable = 0;
-	else {
-		params->SataEnable = dev->enabled;
-		params->SataMode = config->SataMode;
-		params->SataSalpSupport = config->SataSalpSupport;
-		memcpy(params->SataPortsEnable, config->SataPortsEnable,
-			sizeof(params->SataPortsEnable));
-		memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp,
-			sizeof(params->SataPortsDevSlp));
-	}
-
-	/* LAN */
-	dev = pcidev_on_root(PCH_DEV_SLOT_ESPI, 6);
-	if (!dev)
-		params->PchLanEnable = 0;
-	else
-		params->PchLanEnable = dev->enabled;
-
-	/* CNVi */
-	dev = pcidev_path_on_root(PCH_DEVFN_CNVI_WIFI);
-	if (dev)
-		params->CnviMode = dev->enabled;
-	else
-		params->CnviMode = 0;
-
-	/* Legacy 8254 timer support */
-	params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER;
-	params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER;
-
-	/* Enable Hybrid storage auto detection */
-	params->HybridStorageMode = config->HybridStorageMode;
-
-	/* USB4/TBT */
-	for (i = 0; i < ARRAY_SIZE(params->ITbtPcieRootPortEn); i++) {
-		dev = pcidev_on_root(SA_DEV_SLOT_TBT, i);
-		if (dev)
-			params->ITbtPcieRootPortEn[i] = dev->enabled;
-		else
-			params->ITbtPcieRootPortEn[i] = 0;
-	}
-
-	mainboard_silicon_init_params(params);
-}
-
-/* Mainboard GPIO Configuration */
-__weak void mainboard_silicon_init_params(FSP_S_CONFIG *params)
-{
-	printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
-}
-
-/* Return list of SOC LPSS controllers */
-const pci_devfn_t *soc_lpss_controllers_list(size_t *size)
-{
-	*size = ARRAY_SIZE(serial_io_dev);
-	return serial_io_dev;
-}
diff --git a/src/soc/intel/jasperlake/gpio_jsl.c b/src/soc/intel/jasperlake/gpio.c
index afb9f7b3bc..afb9f7b3bc 100644
--- a/src/soc/intel/jasperlake/gpio_jsl.c
+++ b/src/soc/intel/jasperlake/gpio.c
diff --git a/src/soc/intel/jasperlake/gpio_tgl.c b/src/soc/intel/jasperlake/gpio_tgl.c
deleted file mode 100644
index cfdd0ac465..0000000000
--- a/src/soc/intel/jasperlake/gpio_tgl.c
+++ /dev/null
@@ -1,197 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <intelblocks/gpio.h>
-#include <intelblocks/pcr.h>
-#include <soc/pcr_ids.h>
-#include <soc/pmc.h>
-
-/*
- * This file is created based on Intel Tiger Lake Processor PCH Datasheet
- * Document number: 575857
- * Chapter number: 27
- */
-
-static const struct reset_mapping rst_map[] = {
-	{ .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 0U << 30 },
-	{ .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
-	{ .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
-};
-static const struct reset_mapping rst_map_com2[] = {
-	{ .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 },
-	{ .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
-	{ .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
-	{ .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 3U << 30 },
-};
-
-/*
- * This layout matches the Linux kernel pinctrl map for TGL-LP at:
- * linux/drivers/pinctrl/intel/pinctrl-tigerlake.c
- */
-static const struct pad_group tgl_community0_groups[] = {
-	INTEL_GPP(GPP_B0, GPP_B0, GPP_B25),				/* GPP_B */
-	INTEL_GPP(GPP_B0, GPP_T0, GPP_T15),				/* GPP_T */
-	INTEL_GPP(GPP_B0, GPP_A0, GPP_A24),				/* GPP_A */
-};
-
-static const struct pad_group tgl_community1_groups[] = {
-	INTEL_GPP(GPP_S0, GPP_S0, GPP_S7),				/* GPP_S */
-	INTEL_GPP(GPP_S0, GPP_H0, GPP_H23),				/* GPP_H */
-	INTEL_GPP(GPP_S0, GPP_D0, GPP_GSPI2_CLK_LOOPBK),		/* GPP_D */
-	INTEL_GPP(GPP_S0, GPP_U0, GPP_GSPI6_CLK_LOOPBK),		/* GPP_U */
-	INTEL_GPP(GPP_S0, CNV_BTEN, vI2S2_RXD),				/* GPP_VGPIO */
-};
-
-/* This community is not visible to the OS */
-static const struct pad_group tgl_community2_groups[] = {
-	INTEL_GPP(GPD0, GPD0, GPD_DRAM_RESETB),				/* GPD */
-};
-
-static const struct pad_group tgl_community4_groups[] = {
-	INTEL_GPP(GPP_C0, GPP_C0, GPP_C23),				/* GPP_C */
-	INTEL_GPP(GPP_C0, GPP_F0, GPP_F_CLK_LOOPBK),			/* GPP_F */
-	INTEL_GPP(GPP_C0, GPP_L_BKLTEN, GPP_MLK_RSTB),			/* GPP_HVCMOS */
-	INTEL_GPP(GPP_C0, GPP_E0, GPP_E_CLK_LOOPBK),			/* GPP_E */
-	INTEL_GPP(GPP_C0, GPP_JTAG_TDO, GPP_DBG_PMODE),			/* GPP_JTAG */
-};
-
-static const struct pad_group tgl_community5_groups[] = {
-	INTEL_GPP(GPP_R0, GPP_R0, GPP_R7),				/* GPP_R */
-	INTEL_GPP(GPP_R0, GPP_SPI_IO_2, GPP_CLK_LOOPBK),		/* GPP_SPI */
-};
-
-static const struct pad_community tgl_communities[] = {
-	[COMM_0] = { /* GPP B, T, A */
-		.port = PID_GPIOCOM0,
-		.first_pad = GPP_B0,
-		.last_pad = GPP_A24,
-		.num_gpi_regs = NUM_GPIO_COM0_GPI_REGS,
-		.pad_cfg_base = PAD_CFG_BASE,
-		.host_own_reg_0 = HOSTSW_OWN_REG_0,
-		.gpi_int_sts_reg_0 = GPI_INT_STS_0,
-		.gpi_int_en_reg_0 = GPI_INT_EN_0,
-		.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
-		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
-		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
-		.name = "GPP_BTA",
-		.acpi_path = "\\_SB.PCI0.GPIO",
-		.reset_map = rst_map,
-		.num_reset_vals = ARRAY_SIZE(rst_map),
-		.groups = tgl_community0_groups,
-		.num_groups = ARRAY_SIZE(tgl_community0_groups),
-	},
-	[COMM_1] = { /* GPP S, D, H, U, VGPIO */
-		.port = PID_GPIOCOM1,
-		.first_pad = GPP_S0,
-		.last_pad = vI2S2_RXD,
-		.num_gpi_regs = NUM_GPIO_COM1_GPI_REGS,
-		.pad_cfg_base = PAD_CFG_BASE,
-		.host_own_reg_0 = HOSTSW_OWN_REG_0,
-		.gpi_int_sts_reg_0 = GPI_INT_STS_0,
-		.gpi_int_en_reg_0 = GPI_INT_EN_0,
-		.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
-		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
-		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
-		.name = "GPP_SDHU",
-		.acpi_path = "\\_SB.PCI0.GPIO",
-		.reset_map = rst_map,
-		.num_reset_vals = ARRAY_SIZE(rst_map),
-		.groups = tgl_community1_groups,
-		.num_groups = ARRAY_SIZE(tgl_community1_groups),
-	},
-	[COMM_2] = { /* GPD */
-		.port = PID_GPIOCOM2,
-		.first_pad = GPD0,
-		.last_pad = GPD_DRAM_RESETB,
-		.num_gpi_regs = NUM_GPIO_COM2_GPI_REGS,
-		.pad_cfg_base = PAD_CFG_BASE,
-		.host_own_reg_0 = HOSTSW_OWN_REG_0,
-		.gpi_int_sts_reg_0 = GPI_INT_STS_0,
-		.gpi_int_en_reg_0 = GPI_INT_EN_0,
-		.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
-		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
-		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
-		.name = "GPD",
-		.acpi_path = "\\_SB.PCI0.GPIO",
-		.reset_map = rst_map_com2,
-		.num_reset_vals = ARRAY_SIZE(rst_map_com2),
-		.groups = tgl_community2_groups,
-		.num_groups = ARRAY_SIZE(tgl_community2_groups),
-	},
-	[COMM_4] = { /* GPP F, C, HVCOS, E, JTAG */
-		.port = PID_GPIOCOM4,
-		.first_pad = GPP_C0,
-		.last_pad = GPP_DBG_PMODE,
-		.num_gpi_regs = NUM_GPIO_COM4_GPI_REGS,
-		.pad_cfg_base = PAD_CFG_BASE,
-		.host_own_reg_0 = HOSTSW_OWN_REG_0,
-		.gpi_int_sts_reg_0 = GPI_INT_STS_0,
-		.gpi_int_en_reg_0 = GPI_INT_EN_0,
-		.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
-		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
-		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
-		.name = "GPP_FCE",
-		.acpi_path = "\\_SB.PCI0.GPIO",
-		.reset_map = rst_map,
-		.num_reset_vals = ARRAY_SIZE(rst_map),
-		.groups = tgl_community4_groups,
-		.num_groups = ARRAY_SIZE(tgl_community4_groups),
-	},
-	[COMM_5] = { /* GPP R, SPI */
-		.port = PID_GPIOCOM5,
-		.first_pad = GPP_R0,
-		.last_pad = GPP_CLK_LOOPBK,
-		.num_gpi_regs = NUM_GPIO_COM5_GPI_REGS,
-		.pad_cfg_base = PAD_CFG_BASE,
-		.host_own_reg_0 = HOSTSW_OWN_REG_0,
-		.gpi_int_sts_reg_0 = GPI_INT_STS_0,
-		.gpi_int_en_reg_0 = GPI_INT_EN_0,
-		.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
-		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
-		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
-		.name = "GPP_CPU_VBPIO",
-		.acpi_path = "\\_SB.PCI0.GPIO",
-		.reset_map = rst_map,
-		.num_reset_vals = ARRAY_SIZE(rst_map),
-		.groups = tgl_community5_groups,
-		.num_groups = ARRAY_SIZE(tgl_community5_groups),
-	}
-};
-
-const struct pad_community *soc_gpio_get_community(size_t *num_communities)
-{
-	*num_communities = ARRAY_SIZE(tgl_communities);
-	return tgl_communities;
-}
-
-const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num)
-{
-	static const struct pmc_to_gpio_route routes[] = {
-		{ PMC_GPP_B, GPP_B },
-		{ PMC_GPP_T, GPP_T },
-		{ PMC_GPP_A, GPP_A },
-		{ PMC_GPP_R, GPP_R },
-		{ PMC_GPD, GPD },
-		{ PMC_GPP_S, GPP_S },
-		{ PMC_GPP_H, GPP_H },
-		{ PMC_GPP_D, GPP_D },
-		{ PMC_GPP_U, GPP_U },
-		{ PMC_GPP_F, GPP_F },
-		{ PMC_GPP_C, GPP_C },
-		{ PMC_GPP_E, GPP_E },
-	};
-	*num = ARRAY_SIZE(routes);
-	return routes;
-}
diff --git a/src/soc/intel/jasperlake/graphics.c b/src/soc/intel/jasperlake/graphics.c
index fef17e17e8..4f5d573c8b 100644
--- a/src/soc/intel/jasperlake/graphics.c
+++ b/src/soc/intel/jasperlake/graphics.c
@@ -13,12 +13,6 @@
  * GNU General Public License for more details.
  */
 
-/*
- * This file is created based on Intel Tiger Lake Processor SA Datasheet
- * Document number: 571131
- * Chapter number: 4
- */
-
 #include <arch/acpi.h>
 #include <console/console.h>
 #include <fsp/util.h>
diff --git a/src/soc/intel/jasperlake/gspi.c b/src/soc/intel/jasperlake/gspi.c
index 1381fb2499..706eeac854 100644
--- a/src/soc/intel/jasperlake/gspi.c
+++ b/src/soc/intel/jasperlake/gspi.c
@@ -13,12 +13,6 @@
  * GNU General Public License for more details.
  */
 
-/*
- * This file is created based on Intel Tiger Lake Processor PCH Datasheet
- * Document number: 575857
- * Chapter number: 11
- */
-
 #include <intelblocks/gspi.h>
 #include <soc/pci_devs.h>
 
diff --git a/src/soc/intel/jasperlake/i2c.c b/src/soc/intel/jasperlake/i2c.c
index 46bc726726..df95df924a 100644
--- a/src/soc/intel/jasperlake/i2c.c
+++ b/src/soc/intel/jasperlake/i2c.c
@@ -12,12 +12,6 @@
  * GNU General Public License for more details.
  */
 
-/*
- * This file is created based on Intel Tiger Lake Processor PCH Datasheet
- * Document number: 575857
- * Chapter number: 13
- */
-
 #include <device/device.h>
 #include <drivers/i2c/designware/dw_i2c.h>
 #include <soc/pci_devs.h>
diff --git a/src/soc/intel/jasperlake/include/soc/bootblock.h b/src/soc/intel/jasperlake/include/soc/bootblock.h
index 0c8d8c201a..a93cff8dad 100644
--- a/src/soc/intel/jasperlake/include/soc/bootblock.h
+++ b/src/soc/intel/jasperlake/include/soc/bootblock.h
@@ -12,8 +12,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef _SOC_TIGERLAKE_BOOTBLOCK_H_
-#define _SOC_TIGERLAKE_BOOTBLOCK_H_
+#ifndef _SOC_JASPERLAKE_BOOTBLOCK_H_
+#define _SOC_JASPERLAKE_BOOTBLOCK_H_
 
 /* Bootblock pre console init programming */
 void bootblock_cpu_init(void);
diff --git a/src/soc/intel/jasperlake/include/soc/cpu.h b/src/soc/intel/jasperlake/include/soc/cpu.h
index 799382498b..96e29bfcb8 100644
--- a/src/soc/intel/jasperlake/include/soc/cpu.h
+++ b/src/soc/intel/jasperlake/include/soc/cpu.h
@@ -12,8 +12,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef _SOC_TIGERLAKE_CPU_H_
-#define _SOC_TIGERLAKE_CPU_H_
+#ifndef _SOC_JASPERLAKE_CPU_H_
+#define _SOC_JASPERLAKE_CPU_H_
 
 #include <intelblocks/msr.h>
 
diff --git a/src/soc/intel/jasperlake/include/soc/espi.h b/src/soc/intel/jasperlake/include/soc/espi.h
index 3f7e32a717..7303a6d981 100644
--- a/src/soc/intel/jasperlake/include/soc/espi.h
+++ b/src/soc/intel/jasperlake/include/soc/espi.h
@@ -12,14 +12,8 @@
  * GNU General Public License for more details.
  */
 
-/*
- * This file is created based on Intel Tiger Lake Processor PCH Datasheet
- * Document number: 575857
- * Chapter number: 2
- */
-
-#ifndef _SOC_TIGERLAKE_ESPI_H_
-#define _SOC_TIGERLAKE_ESPI_H_
+#ifndef _SOC_JASPERLAKE_ESPI_H_
+#define _SOC_JASPERLAKE_ESPI_H_
 
 #include <stdint.h>
 
@@ -44,15 +38,4 @@
 #define PCCTL			0xE0 /* PCI Clock Control */
 #define   CLKRUN_EN		(1 << 0)
 
-/*
- * This function will help to differentiate between 2 PCH on single type of soc.
- * Since same soc may have LP series pch or H series PCH, we need to
- * differentiate by reading upper 8 bits of PCH device ids.
- *
- * Return:
- *	Return PCH_LP or PCH_H macro in case of respective device ID found.
- *	PCH_UNKNOWN_SERIES in case of invalid device ID.
- */
-uint8_t get_pch_series(void);
-
 #endif
diff --git a/src/soc/intel/jasperlake/include/soc/gpio.h b/src/soc/intel/jasperlake/include/soc/gpio.h
index fb3f42fd67..b24b467939 100644
--- a/src/soc/intel/jasperlake/include/soc/gpio.h
+++ b/src/soc/intel/jasperlake/include/soc/gpio.h
@@ -12,27 +12,17 @@
  * GNU General Public License for more details.
  */
 
-#ifndef _SOC_TIGERLAKE_GPIO_H_
-#define _SOC_TIGERLAKE_GPIO_H_
+#ifndef _SOC_JASPERLAKE_GPIO_H_
+#define _SOC_JASPERLAKE_GPIO_H_
 
 #include <soc/gpio_defs.h>
 #include <intelblocks/gpio.h>
 
-#if CONFIG(SOC_INTEL_TIGERLAKE_COPY)
 
-	#define CROS_GPIO_NAME		"INT34C5"
-	#define CROS_GPIO_COMM0_NAME    "INT34C5:00"
-	#define CROS_GPIO_COMM1_NAME    "INT34C5:01"
-	#define CROS_GPIO_COMM4_NAME    "INT34C5:02"
-	#define CROS_GPIO_COMM5_NAME    "INT34C5:03"
-
-#elif CONFIG(SOC_INTEL_JASPERLAKE_COPY)
-
-	#define CROS_GPIO_NAME		"INT34C8"
-	#define CROS_GPIO_COMM0_NAME    "INT34C8:00"
-	#define CROS_GPIO_COMM1_NAME    "INT34C8:01"
-	#define CROS_GPIO_COMM4_NAME    "INT34C8:02"
-	#define CROS_GPIO_COMM5_NAME    "INT34C8:03"
-#endif
+#define CROS_GPIO_NAME		"INT34C8"
+#define CROS_GPIO_COMM0_NAME    "INT34C8:00"
+#define CROS_GPIO_COMM1_NAME    "INT34C8:01"
+#define CROS_GPIO_COMM4_NAME    "INT34C8:02"
+#define CROS_GPIO_COMM5_NAME    "INT34C8:03"
 
 #endif
diff --git a/src/soc/intel/jasperlake/include/soc/gpio_defs.h b/src/soc/intel/jasperlake/include/soc/gpio_defs.h
index 2898c12ee0..c030561a2e 100644
--- a/src/soc/intel/jasperlake/include/soc/gpio_defs.h
+++ b/src/soc/intel/jasperlake/include/soc/gpio_defs.h
@@ -12,12 +12,261 @@
  * GNU General Public License for more details.
  */
 
-#ifndef _SOC_TIGERLAKE_GPIO_DEFS_H_
-#define _SOC_TIGERLAKE_GPIO_DEFS_H_
+#ifndef _SOC_JASPERLAKE_GPIO_DEFS_H_
+#define _SOC_JASPERLAKE_GPIO_DEFS_H_
 
-#if CONFIG(SOC_INTEL_TIGERLAKE_COPY)
-	#include <soc/gpio_defs_tgl.h>
-#elif CONFIG(SOC_INTEL_JASPERLAKE_COPY)
-	#include <soc/gpio_defs_jsl.h>
+#ifndef __ACPI__
+#include <stddef.h>
 #endif
+#include <soc/gpio_soc_defs.h>
+
+
+#define GPIO_NUM_PAD_CFG_REGS   4 /* DW0, DW1, DW2, DW3 */
+
+#define NUM_GPIO_COMx_GPI_REGS(n)	\
+		(ALIGN_UP((n), GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP)
+
+#define NUM_GPIO_COM0_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM0_PADS)
+#define NUM_GPIO_COM1_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM1_PADS)
+#define NUM_GPIO_COM2_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM2_PADS)
+#define NUM_GPIO_COM4_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM4_PADS)
+#define NUM_GPIO_COM5_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM5_PADS)
+
+#define NUM_GPI_STATUS_REGS	\
+		((NUM_GPIO_COM0_GPI_REGS) +\
+		(NUM_GPIO_COM1_GPI_REGS) +\
+		(NUM_GPIO_COM2_GPI_REGS) +\
+		(NUM_GPIO_COM4_GPI_REGS) +\
+		(NUM_GPIO_COM5_GPI_REGS))
+/*
+ * IOxAPIC IRQs for the GPIOs
+ */
+
+/* Group F */
+#define GPP_F0_IRQ				0x40
+#define GPP_F1_IRQ				0x41
+#define GPP_F2_IRQ				0x42
+#define GPP_F3_IRQ				0x43
+#define GPP_F4_IRQ				0x44
+#define GPP_F5_IRQ				0x45
+#define GPP_F6_IRQ				0x46
+#define GPP_F7_IRQ				0x47
+#define GPP_F8_IRQ				0x48
+#define GPP_F9_IRQ				0x49
+#define GPP_F10_IRQ				0x4a
+#define GPP_F11_IRQ				0x4b
+#define GPP_F12_IRQ				0x4c
+#define GPP_F13_IRQ				0x4d
+#define GPP_F14_IRQ				0x4e
+#define GPP_F15_IRQ				0x4f
+#define GPP_F16_IRQ				0x50
+#define GPP_F17_IRQ				0x51
+#define GPP_F18_IRQ				0x52
+#define GPP_F19_IRQ				0x53
+
+/* Group G */
+#define GPP_G0_IRQ				0x18
+#define GPP_G1_IRQ				0x19
+#define GPP_G2_IRQ				0x1a
+#define GPP_G3_IRQ				0x1b
+#define GPP_G4_IRQ				0x1c
+#define GPP_G5_IRQ				0x1d
+#define GPP_G6_IRQ				0x1e
+#define GPP_G7_IRQ				0x1f
+
+/* Group B */
+#define GPP_B0_IRQ				0x20
+#define GPP_B1_IRQ				0x21
+#define GPP_B2_IRQ				0x22
+#define GPP_B3_IRQ				0x23
+#define GPP_B4_IRQ				0x24
+#define GPP_B5_IRQ				0x25
+#define GPP_B6_IRQ				0x26
+#define GPP_B7_IRQ				0x27
+#define GPP_B8_IRQ				0x28
+#define GPP_B9_IRQ				0x29
+#define GPP_B10_IRQ				0x2a
+#define GPP_B11_IRQ				0x2b
+#define GPP_B12_IRQ				0x2c
+#define GPP_B13_IRQ				0x2d
+#define GPP_B14_IRQ				0x2e
+#define GPP_B15_IRQ				0x2f
+#define GPP_B16_IRQ				0x30
+#define GPP_B17_IRQ				0x31
+#define GPP_B18_IRQ				0x32
+#define GPP_B19_IRQ				0x33
+#define GPP_B20_IRQ				0x34
+#define GPP_B21_IRQ				0x35
+#define GPP_B22_IRQ				0x36
+#define GPP_B23_IRQ				0x37
+
+/* Group A */
+#define GPP_A0_IRQ				0x38
+#define GPP_A1_IRQ				0x39
+#define GPP_A2_IRQ				0x3a
+#define GPP_A3_IRQ				0x3b
+#define GPP_A4_IRQ				0x3c
+#define GPP_A5_IRQ				0x3d
+#define GPP_A6_IRQ				0x3e
+#define GPP_A7_IRQ				0x3f
+#define GPP_A8_IRQ				0x40
+#define GPP_A9_IRQ				0x41
+#define GPP_A10_IRQ				0x42
+#define GPP_A11_IRQ				0x43
+#define GPP_A12_IRQ				0x44
+#define GPP_A13_IRQ				0x45
+#define GPP_A14_IRQ				0x46
+#define GPP_A15_IRQ				0x47
+#define GPP_A16_IRQ				0x48
+#define GPP_A17_IRQ				0x49
+#define GPP_A18_IRQ				0x4a
+#define GPP_A19_IRQ				0x4b
+
+/* Group H */
+#define GPP_H0_IRQ				0x70
+#define GPP_H1_IRQ				0x71
+#define GPP_H2_IRQ				0x72
+#define GPP_H3_IRQ				0x73
+#define GPP_H4_IRQ				0x74
+#define GPP_H5_IRQ				0x75
+#define GPP_H6_IRQ				0x76
+#define GPP_H7_IRQ				0x77
+#define GPP_H8_IRQ				0x18
+#define GPP_H9_IRQ				0x19
+#define GPP_H10_IRQ				0x1a
+#define GPP_H11_IRQ				0x1b
+#define GPP_H12_IRQ				0x1c
+#define GPP_H13_IRQ				0x1d
+#define GPP_H14_IRQ				0x1e
+#define GPP_H15_IRQ				0x1f
+#define GPP_H16_IRQ				0x20
+#define GPP_H17_IRQ				0x21
+#define GPP_H18_IRQ				0x22
+#define GPP_H19_IRQ				0x23
+#define GPP_H20_IRQ				0x24
+#define GPP_H21_IRQ				0x25
+#define GPP_H22_IRQ				0x26
+#define GPP_H23_IRQ				0x27
+
+/* Group D */
+#define GPP_D0_IRQ				0x28
+#define GPP_D1_IRQ				0x29
+#define GPP_D2_IRQ				0x2a
+#define GPP_D3_IRQ				0x2b
+#define GPP_D4_IRQ				0x2c
+#define GPP_D5_IRQ				0x2d
+#define GPP_D6_IRQ				0x2e
+#define GPP_D7_IRQ				0x2f
+#define GPP_D8_IRQ				0x30
+#define GPP_D9_IRQ				0x31
+#define GPP_D10_IRQ				0x32
+#define GPP_D11_IRQ				0x33
+#define GPP_D12_IRQ				0x34
+#define GPP_D13_IRQ				0x35
+#define GPP_D14_IRQ				0x36
+#define GPP_D15_IRQ				0x37
+#define GPP_D16_IRQ				0x38
+#define GPP_D17_IRQ				0x39
+#define GPP_D18_IRQ				0x3a
+#define GPP_D19_IRQ				0x3b
+#define GPP_D20_IRQ				0x3c
+#define GPP_D21_IRQ				0x3d
+#define GPP_D22_IRQ				0x3e
+#define GPP_D23_IRQ				0x3f
+
+/* Group GPD */
+#define GPD0_IRQ				0x64
+#define GPD1_IRQ				0x65
+#define GPD2_IRQ				0x66
+#define GPD3_IRQ				0x67
+#define GPD4_IRQ				0x68
+#define GPD5_IRQ				0x69
+#define GPD6_IRQ				0x6a
+#define GPD7_IRQ				0x6b
+#define GPD8_IRQ				0x6c
+#define GPD9_IRQ				0x6d
+#define GPD10_IRQ				0x6e
+
+/* Group C */
+#define GPP_C0_IRQ				0x5a
+#define GPP_C1_IRQ				0x5b
+#define GPP_C2_IRQ				0x5c
+#define GPP_C3_IRQ				0x5d
+#define GPP_C4_IRQ				0x5e
+#define GPP_C5_IRQ				0x5f
+#define GPP_C6_IRQ				0x60
+#define GPP_C7_IRQ				0x61
+#define GPP_C8_IRQ				0x62
+#define GPP_C9_IRQ				0x63
+#define GPP_C10_IRQ				0x64
+#define GPP_C11_IRQ				0x65
+#define GPP_C12_IRQ				0x66
+#define GPP_C13_IRQ				0x67
+#define GPP_C14_IRQ				0x68
+#define GPP_C15_IRQ				0x69
+#define GPP_C16_IRQ				0x6a
+#define GPP_C17_IRQ				0x6b
+#define GPP_C18_IRQ				0x6c
+#define GPP_C19_IRQ				0x6d
+#define GPP_C20_IRQ				0x6e
+#define GPP_C21_IRQ				0x6f
+#define GPP_C22_IRQ				0x70
+#define GPP_C23_IRQ				0x71
+/* Group E */
+#define GPP_E0_IRQ				0x72
+#define GPP_E1_IRQ				0x73
+#define GPP_E2_IRQ				0x74
+#define GPP_E3_IRQ				0x75
+#define GPP_E4_IRQ				0x76
+#define GPP_E5_IRQ				0x77
+#define GPP_E6_IRQ				0x18
+#define GPP_E7_IRQ				0x19
+#define GPP_E8_IRQ				0x1a
+#define GPP_E9_IRQ				0x1b
+#define GPP_E10_IRQ				0x1c
+#define GPP_E11_IRQ				0x1d
+#define GPP_E12_IRQ				0x1e
+#define GPP_E13_IRQ				0x1f
+#define GPP_E14_IRQ				0x20
+#define GPP_E15_IRQ				0x21
+#define GPP_E16_IRQ				0x22
+#define GPP_E17_IRQ				0x23
+#define GPP_E18_IRQ				0x24
+#define GPP_E19_IRQ				0x25
+#define GPP_E20_IRQ				0x26
+#define GPP_E21_IRQ				0x27
+#define GPP_E22_IRQ				0x28
+#define GPP_E23_IRQ				0x29
+
+/* Group R*/
+#define GPP_R0_IRQ				0x50
+#define GPP_R1_IRQ				0x51
+#define GPP_R2_IRQ				0x52
+#define GPP_R3_IRQ				0x53
+#define GPP_R4_IRQ				0x54
+#define GPP_R5_IRQ				0x55
+#define GPP_R6_IRQ				0x56
+#define GPP_R7_IRQ				0x57
+
+/* Group S */
+#define GPP_S0_IRQ				0x5c
+#define GPP_S1_IRQ				0x5d
+#define GPP_S2_IRQ				0x5e
+#define GPP_S3_IRQ				0x5f
+#define GPP_S4_IRQ				0x60
+#define GPP_S5_IRQ				0x61
+#define GPP_S6_IRQ				0x62
+#define GPP_S7_IRQ				0x63
+
+/* Register defines. */
+#define GPIO_MISCCFG				0x10
+#define GPE_DW_SHIFT				8
+#define GPE_DW_MASK				0xfff00
+#define HOSTSW_OWN_REG_0			0xc0
+#define GPI_INT_STS_0				0x100
+#define GPI_INT_EN_0				0x120
+#define GPI_SMI_STS_0				0x180
+#define GPI_SMI_EN_0				0x1a0
+#define PAD_CFG_BASE				0x600
+
 #endif
diff --git a/src/soc/intel/jasperlake/include/soc/gpio_defs_jsl.h b/src/soc/intel/jasperlake/include/soc/gpio_defs_jsl.h
deleted file mode 100644
index 69ed539cae..0000000000
--- a/src/soc/intel/jasperlake/include/soc/gpio_defs_jsl.h
+++ /dev/null
@@ -1,272 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef _SOC_JASPERLAKE_GPIO_DEFS_H_
-#define _SOC_JASPERLAKE_GPIO_DEFS_H_
-
-#ifndef __ACPI__
-#include <stddef.h>
-#endif
-#include <soc/gpio_soc_defs_jsl.h>
-
-
-#define GPIO_NUM_PAD_CFG_REGS   4 /* DW0, DW1, DW2, DW3 */
-
-#define NUM_GPIO_COMx_GPI_REGS(n)	\
-		(ALIGN_UP((n), GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP)
-
-#define NUM_GPIO_COM0_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM0_PADS)
-#define NUM_GPIO_COM1_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM1_PADS)
-#define NUM_GPIO_COM2_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM2_PADS)
-#define NUM_GPIO_COM4_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM4_PADS)
-#define NUM_GPIO_COM5_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM5_PADS)
-
-#define NUM_GPI_STATUS_REGS	\
-		((NUM_GPIO_COM0_GPI_REGS) +\
-		(NUM_GPIO_COM1_GPI_REGS) +\
-		(NUM_GPIO_COM2_GPI_REGS) +\
-		(NUM_GPIO_COM4_GPI_REGS) +\
-		(NUM_GPIO_COM5_GPI_REGS))
-/*
- * IOxAPIC IRQs for the GPIOs
- */
-
-/* Group F */
-#define GPP_F0_IRQ				0x40
-#define GPP_F1_IRQ				0x41
-#define GPP_F2_IRQ				0x42
-#define GPP_F3_IRQ				0x43
-#define GPP_F4_IRQ				0x44
-#define GPP_F5_IRQ				0x45
-#define GPP_F6_IRQ				0x46
-#define GPP_F7_IRQ				0x47
-#define GPP_F8_IRQ				0x48
-#define GPP_F9_IRQ				0x49
-#define GPP_F10_IRQ				0x4a
-#define GPP_F11_IRQ				0x4b
-#define GPP_F12_IRQ				0x4c
-#define GPP_F13_IRQ				0x4d
-#define GPP_F14_IRQ				0x4e
-#define GPP_F15_IRQ				0x4f
-#define GPP_F16_IRQ				0x50
-#define GPP_F17_IRQ				0x51
-#define GPP_F18_IRQ				0x52
-#define GPP_F19_IRQ				0x53
-
-/* Group G */
-#define GPP_G0_IRQ				0x18
-#define GPP_G1_IRQ				0x19
-#define GPP_G2_IRQ				0x1a
-#define GPP_G3_IRQ				0x1b
-#define GPP_G4_IRQ				0x1c
-#define GPP_G5_IRQ				0x1d
-#define GPP_G6_IRQ				0x1e
-#define GPP_G7_IRQ				0x1f
-
-/* Group B */
-#define GPP_B0_IRQ				0x20
-#define GPP_B1_IRQ				0x21
-#define GPP_B2_IRQ				0x22
-#define GPP_B3_IRQ				0x23
-#define GPP_B4_IRQ				0x24
-#define GPP_B5_IRQ				0x25
-#define GPP_B6_IRQ				0x26
-#define GPP_B7_IRQ				0x27
-#define GPP_B8_IRQ				0x28
-#define GPP_B9_IRQ				0x29
-#define GPP_B10_IRQ				0x2a
-#define GPP_B11_IRQ				0x2b
-#define GPP_B12_IRQ				0x2c
-#define GPP_B13_IRQ				0x2d
-#define GPP_B14_IRQ				0x2e
-#define GPP_B15_IRQ				0x2f
-#define GPP_B16_IRQ				0x30
-#define GPP_B17_IRQ				0x31
-#define GPP_B18_IRQ				0x32
-#define GPP_B19_IRQ				0x33
-#define GPP_B20_IRQ				0x34
-#define GPP_B21_IRQ				0x35
-#define GPP_B22_IRQ				0x36
-#define GPP_B23_IRQ				0x37
-
-/* Group A */
-#define GPP_A0_IRQ				0x38
-#define GPP_A1_IRQ				0x39
-#define GPP_A2_IRQ				0x3a
-#define GPP_A3_IRQ				0x3b
-#define GPP_A4_IRQ				0x3c
-#define GPP_A5_IRQ				0x3d
-#define GPP_A6_IRQ				0x3e
-#define GPP_A7_IRQ				0x3f
-#define GPP_A8_IRQ				0x40
-#define GPP_A9_IRQ				0x41
-#define GPP_A10_IRQ				0x42
-#define GPP_A11_IRQ				0x43
-#define GPP_A12_IRQ				0x44
-#define GPP_A13_IRQ				0x45
-#define GPP_A14_IRQ				0x46
-#define GPP_A15_IRQ				0x47
-#define GPP_A16_IRQ				0x48
-#define GPP_A17_IRQ				0x49
-#define GPP_A18_IRQ				0x4a
-#define GPP_A19_IRQ				0x4b
-
-/* Group H */
-#define GPP_H0_IRQ				0x70
-#define GPP_H1_IRQ				0x71
-#define GPP_H2_IRQ				0x72
-#define GPP_H3_IRQ				0x73
-#define GPP_H4_IRQ				0x74
-#define GPP_H5_IRQ				0x75
-#define GPP_H6_IRQ				0x76
-#define GPP_H7_IRQ				0x77
-#define GPP_H8_IRQ				0x18
-#define GPP_H9_IRQ				0x19
-#define GPP_H10_IRQ				0x1a
-#define GPP_H11_IRQ				0x1b
-#define GPP_H12_IRQ				0x1c
-#define GPP_H13_IRQ				0x1d
-#define GPP_H14_IRQ				0x1e
-#define GPP_H15_IRQ				0x1f
-#define GPP_H16_IRQ				0x20
-#define GPP_H17_IRQ				0x21
-#define GPP_H18_IRQ				0x22
-#define GPP_H19_IRQ				0x23
-#define GPP_H20_IRQ				0x24
-#define GPP_H21_IRQ				0x25
-#define GPP_H22_IRQ				0x26
-#define GPP_H23_IRQ				0x27
-
-/* Group D */
-#define GPP_D0_IRQ				0x28
-#define GPP_D1_IRQ				0x29
-#define GPP_D2_IRQ				0x2a
-#define GPP_D3_IRQ				0x2b
-#define GPP_D4_IRQ				0x2c
-#define GPP_D5_IRQ				0x2d
-#define GPP_D6_IRQ				0x2e
-#define GPP_D7_IRQ				0x2f
-#define GPP_D8_IRQ				0x30
-#define GPP_D9_IRQ				0x31
-#define GPP_D10_IRQ				0x32
-#define GPP_D11_IRQ				0x33
-#define GPP_D12_IRQ				0x34
-#define GPP_D13_IRQ				0x35
-#define GPP_D14_IRQ				0x36
-#define GPP_D15_IRQ				0x37
-#define GPP_D16_IRQ				0x38
-#define GPP_D17_IRQ				0x39
-#define GPP_D18_IRQ				0x3a
-#define GPP_D19_IRQ				0x3b
-#define GPP_D20_IRQ				0x3c
-#define GPP_D21_IRQ				0x3d
-#define GPP_D22_IRQ				0x3e
-#define GPP_D23_IRQ				0x3f
-
-/* Group GPD */
-#define GPD0_IRQ				0x64
-#define GPD1_IRQ				0x65
-#define GPD2_IRQ				0x66
-#define GPD3_IRQ				0x67
-#define GPD4_IRQ				0x68
-#define GPD5_IRQ				0x69
-#define GPD6_IRQ				0x6a
-#define GPD7_IRQ				0x6b
-#define GPD8_IRQ				0x6c
-#define GPD9_IRQ				0x6d
-#define GPD10_IRQ				0x6e
-
-/* Group C */
-#define GPP_C0_IRQ				0x5a
-#define GPP_C1_IRQ				0x5b
-#define GPP_C2_IRQ				0x5c
-#define GPP_C3_IRQ				0x5d
-#define GPP_C4_IRQ				0x5e
-#define GPP_C5_IRQ				0x5f
-#define GPP_C6_IRQ				0x60
-#define GPP_C7_IRQ				0x61
-#define GPP_C8_IRQ				0x62
-#define GPP_C9_IRQ				0x63
-#define GPP_C10_IRQ				0x64
-#define GPP_C11_IRQ				0x65
-#define GPP_C12_IRQ				0x66
-#define GPP_C13_IRQ				0x67
-#define GPP_C14_IRQ				0x68
-#define GPP_C15_IRQ				0x69
-#define GPP_C16_IRQ				0x6a
-#define GPP_C17_IRQ				0x6b
-#define GPP_C18_IRQ				0x6c
-#define GPP_C19_IRQ				0x6d
-#define GPP_C20_IRQ				0x6e
-#define GPP_C21_IRQ				0x6f
-#define GPP_C22_IRQ				0x70
-#define GPP_C23_IRQ				0x71
-/* Group E */
-#define GPP_E0_IRQ				0x72
-#define GPP_E1_IRQ				0x73
-#define GPP_E2_IRQ				0x74
-#define GPP_E3_IRQ				0x75
-#define GPP_E4_IRQ				0x76
-#define GPP_E5_IRQ				0x77
-#define GPP_E6_IRQ				0x18
-#define GPP_E7_IRQ				0x19
-#define GPP_E8_IRQ				0x1a
-#define GPP_E9_IRQ				0x1b
-#define GPP_E10_IRQ				0x1c
-#define GPP_E11_IRQ				0x1d
-#define GPP_E12_IRQ				0x1e
-#define GPP_E13_IRQ				0x1f
-#define GPP_E14_IRQ				0x20
-#define GPP_E15_IRQ				0x21
-#define GPP_E16_IRQ				0x22
-#define GPP_E17_IRQ				0x23
-#define GPP_E18_IRQ				0x24
-#define GPP_E19_IRQ				0x25
-#define GPP_E20_IRQ				0x26
-#define GPP_E21_IRQ				0x27
-#define GPP_E22_IRQ				0x28
-#define GPP_E23_IRQ				0x29
-
-/* Group R*/
-#define GPP_R0_IRQ				0x50
-#define GPP_R1_IRQ				0x51
-#define GPP_R2_IRQ				0x52
-#define GPP_R3_IRQ				0x53
-#define GPP_R4_IRQ				0x54
-#define GPP_R5_IRQ				0x55
-#define GPP_R6_IRQ				0x56
-#define GPP_R7_IRQ				0x57
-
-/* Group S */
-#define GPP_S0_IRQ				0x5c
-#define GPP_S1_IRQ				0x5d
-#define GPP_S2_IRQ				0x5e
-#define GPP_S3_IRQ				0x5f
-#define GPP_S4_IRQ				0x60
-#define GPP_S5_IRQ				0x61
-#define GPP_S6_IRQ				0x62
-#define GPP_S7_IRQ				0x63
-
-/* Register defines. */
-#define GPIO_MISCCFG				0x10
-#define GPE_DW_SHIFT				8
-#define GPE_DW_MASK				0xfff00
-#define HOSTSW_OWN_REG_0			0xc0
-#define GPI_INT_STS_0				0x100
-#define GPI_INT_EN_0				0x120
-#define GPI_SMI_STS_0				0x180
-#define GPI_SMI_EN_0				0x1a0
-#define PAD_CFG_BASE				0x600
-
-#endif
diff --git a/src/soc/intel/jasperlake/include/soc/gpio_defs_tgl.h b/src/soc/intel/jasperlake/include/soc/gpio_defs_tgl.h
deleted file mode 100644
index 35a15ded66..0000000000
--- a/src/soc/intel/jasperlake/include/soc/gpio_defs_tgl.h
+++ /dev/null
@@ -1,314 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef _SOC_TIGERLAKE_GPIO_DEFS_TGL_H_
-#define _SOC_TIGERLAKE_GPIO_DEFS_TGL_H_
-
-#ifndef __ACPI__
-#include <stddef.h>
-#endif
-#include <soc/gpio_soc_defs.h>
-
-#define GPIO_NUM_PAD_CFG_REGS   4 /* DW0, DW1, DW2, DW3 */
-
-#define NUM_GPIO_COMx_GPI_REGS(n)	\
-		(ALIGN_UP((n), GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP)
-
-#define NUM_GPIO_COM0_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM0_PADS)
-#define NUM_GPIO_COM1_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM1_PADS)
-#define NUM_GPIO_COM2_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM2_PADS)
-#define NUM_GPIO_COM4_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM4_PADS)
-#define NUM_GPIO_COM5_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM5_PADS)
-
-#define NUM_GPI_STATUS_REGS	\
-		((NUM_GPIO_COM0_GPI_REGS) +\
-		(NUM_GPIO_COM1_GPI_REGS) +\
-		(NUM_GPIO_COM2_GPI_REGS) +\
-		(NUM_GPIO_COM4_GPI_REGS) +\
-		(NUM_GPIO_COM5_GPI_REGS))
-/*
- * IOxAPIC IRQs for the GPIOs
- */
-
-/* Group B */
-#define GPP_B0_IRQ				0x18
-#define GPP_B1_IRQ				0x19
-#define GPP_B2_IRQ				0x1A
-#define GPP_B3_IRQ				0x1B
-#define GPP_B4_IRQ				0x1C
-#define GPP_B5_IRQ				0x1D
-#define GPP_B6_IRQ				0x1E
-#define GPP_B7_IRQ				0x1F
-#define GPP_B8_IRQ				0x20
-#define GPP_B9_IRQ				0x21
-#define GPP_B10_IRQ				0x22
-#define GPP_B11_IRQ				0x23
-#define GPP_B12_IRQ				0x24
-#define GPP_B13_IRQ				0x25
-#define GPP_B14_IRQ				0x26
-#define GPP_B15_IRQ				0x27
-#define GPP_B16_IRQ				0x28
-#define GPP_B17_IRQ				0x29
-#define GPP_B18_IRQ				0x2A
-#define GPP_B19_IRQ				0x2B
-#define GPP_B20_IRQ				0x2C
-#define GPP_B21_IRQ				0x2D
-#define GPP_B22_IRQ				0x2E
-#define GPP_B23_IRQ				0x2F
-
-/* Group T */
-#define GPP_T0_IRQ				0x30
-#define GPP_T1_IRQ				0x31
-#define GPP_T2_IRQ				0x32
-#define GPP_T3_IRQ				0x33
-#define GPP_T4_IRQ				0x34
-#define GPP_T5_IRQ				0x35
-#define GPP_T6_IRQ				0x36
-#define GPP_T7_IRQ				0x37
-#define GPP_T8_IRQ				0x38
-#define GPP_T9_IRQ				0x39
-#define GPP_T10_IRQ				0x3A
-#define GPP_T11IRQ				0x3B
-#define GPP_T12_IRQ				0x3C
-#define GPP_T13_IRQ				0x3D
-#define GPP_T14_IRQ				0x3E
-#define GPP_T15_IRQ				0x3F
-
-/* Group A */
-#define GPP_A0_IRQ				0x40
-#define GPP_A1_IRQ				0x41
-#define GPP_A2_IRQ				0x42
-#define GPP_A3_IRQ				0x43
-#define GPP_A4_IRQ				0x44
-#define GPP_A5_IRQ				0x45
-#define GPP_A6_IRQ				0x46
-#define GPP_A7_IRQ				0x47
-#define GPP_A8_IRQ				0x48
-#define GPP_A9_IRQ				0x49
-#define GPP_A10_IRQ				0x4A
-#define GPP_A11_IRQ				0x4B
-#define GPP_A12_IRQ				0x4C
-#define GPP_A13_IRQ				0x4D
-#define GPP_A14_IRQ				0x4E
-#define GPP_A15_IRQ				0x4F
-#define GPP_A16_IRQ				0x50
-#define GPP_A17_IRQ				0x51
-#define GPP_A18_IRQ				0x52
-#define GPP_A19_IRQ				0x53
-#define GPP_A20_IRQ				0x54
-#define GPP_A21_IRQ				0x55
-#define GPP_A22_IRQ				0x56
-#define GPP_A23_IRQ				0x57
-
-/* Group R */
-#define GPP_R0_IRQ				0x58
-#define GPP_R1_IRQ				0x59
-#define GPP_R2_IRQ				0x5A
-#define GPP_R3_IRQ				0x5B
-#define GPP_R4_IRQ				0x5C
-#define GPP_R5_IRQ				0x5D
-#define GPP_R6_IRQ				0x5E
-#define GPP_R7_IRQ				0x5F
-
-
-/* Group D */
-#define GPD0_IRQ				0x60
-#define GPD1_IRQ				0x61
-#define GPD2_IRQ				0x62
-#define GPD3_IRQ				0x63
-#define GPD4_IRQ				0x64
-#define GPD5_IRQ				0x65
-#define GPD6_IRQ				0x66
-#define GPD7_IRQ				0x67
-#define GPD8_IRQ				0x68
-#define GPD9_IRQ				0x69
-#define GPD10_IRQ				0x6A
-#define GPD11_IRQ				0x6B
-
-/* Group S */
-#define GPP_S0_IRQ				0x6C
-#define GPP_S1_IRQ				0x6D
-#define GPP_S2_IRQ				0x6E
-#define GPP_S3_IRQ				0x6F
-#define GPP_S4_IRQ				0x70
-#define GPP_S5_IRQ				0x71
-#define GPP_S6_IRQ				0x72
-#define GPP_S7_IRQ				0x73
-
-/* Group H */
-#define GPP_H0_IRQ				0x74
-#define GPP_H1_IRQ				0x75
-#define GPP_H2_IRQ				0x76
-#define GPP_H3_IRQ				0x77
-#define GPP_H4_IRQ				0x18
-#define GPP_H5_IRQ				0x19
-#define GPP_H6_IRQ				0x1A
-#define GPP_H7_IRQ				0x1B
-#define GPP_H8_IRQ				0x1C
-#define GPP_H9_IRQ				0x1D
-#define GPP_H10_IRQ				0x1E
-#define GPP_H11_IRQ				0x1F
-#define GPP_H12_IRQ				0x20
-#define GPP_H13_IRQ				0x21
-#define GPP_H14_IRQ				0x22
-#define GPP_H15_IRQ				0x23
-#define GPP_H16_IRQ				0x24
-#define GPP_H17_IRQ				0x25
-#define GPP_H18_IRQ				0x26
-#define GPP_H19_IRQ				0x27
-#define GPP_H20_IRQ				0x28
-#define GPP_H21_IRQ				0x29
-#define GPP_H22_IRQ				0x2A
-#define GPP_H23_IRQ				0x2B
-
-/* Group D */
-#define GPP_D0_IRQ				0x2C
-#define GPP_D1_IRQ				0x2D
-#define GPP_D2_IRQ				0x2E
-#define GPP_D3_IRQ				0x2F
-#define GPP_D4_IRQ				0x30
-#define GPP_D5_IRQ				0x31
-#define GPP_D6_IRQ				0x32
-#define GPP_D7_IRQ				0x33
-#define GPP_D8_IRQ				0x34
-#define GPP_D9_IRQ				0x35
-#define GPP_D10_IRQ				0x36
-#define GPP_D11_IRQ				0x37
-#define GPP_D12_IRQ				0x38
-#define GPP_D13_IRQ				0x39
-#define GPP_D14_IRQ				0x3A
-#define GPP_D15_IRQ				0x3B
-#define GPP_D16_IRQ				0x3C
-#define GPP_D17_IRQ				0x3D
-#define GPP_D18_IRQ				0x3E
-#define GPP_D19_IRQ				0x3F
-
-
-/* Group U */
-#define GPP_U0_IRQ				0x40
-#define GPP_U1IRQ				0x41
-#define GPP_U2_IRQ				0x42
-#define GPP_U3_IRQ				0x43
-#define GPP_U4_IRQ				0x44
-#define GPP_U5_IRQ				0x45
-#define GPP_U6_IRQ				0x46
-#define GPP_U7_IRQ				0x47
-#define GPP_U8_IRQ				0x48
-#define GPP_U9_IRQ				0x49
-#define GPP_U10_IRQ				0x4A
-#define GPP_U11_IRQ				0x4B
-#define GPP_U12_IRQ				0x4C
-#define GPP_U13_IRQ				0x4D
-#define GPP_U14_IRQ				0x4E
-#define GPP_U15_IRQ				0x4F
-#define GPP_U16_IRQ				0x50
-#define GPP_U17_IRQ				0x51
-#define GPP_U18_IRQ				0x52
-#define GPP_U19_IRQ				0x53
-
-
-#define GPP_VGPIO4_IRQ				0x54
-
-/* Group F */
-#define GPP_F0_IRQ				0x56
-#define GPP_F1_IRQ				0x57
-#define GPP_F2_IRQ				0x58
-#define GPP_F3_IRQ				0x59
-#define GPP_F4_IRQ				0x5A
-#define GPP_F5_IRQ				0x5B
-#define GPP_F6_IRQ				0x5C
-#define GPP_F7_IRQ				0x5D
-#define GPP_F8_IRQ				0x5E
-#define GPP_F9_IRQ				0x5F
-#define GPP_F10_IRQ				0x60
-#define GPP_F11_IRQ				0x61
-#define GPP_F12_IRQ				0x62
-#define GPP_F13_IRQ				0x63
-#define GPP_F14_IRQ				0x64
-#define GPP_F15_IRQ				0x65
-#define GPP_F16_IRQ				0x66
-#define GPP_F17_IRQ				0x67
-#define GPP_F18_IRQ				0x68
-#define GPP_F19_IRQ				0x69
-#define GPP_F20_IRQ				0x6A
-#define GPP_F21_IRQ				0x6B
-#define GPP_F22_IRQ				0x6C
-#define GPP_F23_IRQ				0x6D
-
-/* Group C */
-#define GPP_C0_iIRQ				0x6E
-#define GPP_C1_IRQ				0x6F
-#define GPP_C2_IRQ				0x70
-#define GPP_C3_IRQ				0x71
-#define GPP_C4_IRQ				0x72
-#define GPP_C5_IRQ				0x73
-#define GPP_C6_IRQ				0x74
-#define GPP_C7_IRQ				0x75
-#define GPP_C8_IRQ				0x76
-#define GPP_C9_IRQ				0x77
-#define GPP_C10_IRQ				0x18
-#define GPP_C11_IRQ				0x19
-#define GPP_C12_IRQ				0x1A
-#define GPP_C13_IRQ				0x1B
-#define GPP_C14_IRQ				0x1C
-#define GPP_C15_IRQ				0x1D
-#define GPP_C16_IRQ				0x1E
-#define GPP_C17_IRQ				0x1F
-#define GPP_C18_IRQ				0x20
-#define GPP_C19_IRQ				0x21
-#define GPP_C20_IRQ				0x22
-#define GPP_C21_IRQ				0x23
-#define GPP_C22_IRQ				0x24
-#define GPP_C23_IRQ				0x25
-
-
-
-/* Group E */
-#define GPP_E0_IRQ				0x26
-#define GPP_E1_IRQ				0x27
-#define GPP_E2_IRQ				0x28
-#define GPP_E3_IRQ				0x29
-#define GPP_E4_IRQ				0x30
-#define GPP_E5_IRQ				0x31
-#define GPP_E6_IRQ				0x32
-#define GPP_E7_IRQ				0x33
-#define GPP_E8_IRQ				0x34
-#define GPP_E9_IRQ				0x35
-#define GPP_E10_IRQ				0x36
-#define GPP_E11_IRQ				0x37
-#define GPP_E12_IRQ				0x38
-#define GPP_E13_IRQ				0x39
-#define GPP_E14_IRQ				0x3A
-#define GPP_E15_IRQ				0x3B
-#define GPP_E16_IRQ				0x3C
-#define GPP_E17_IRQ				0x3D
-#define GPP_E18_IRQ				0x3E
-#define GPP_E19_IRQ				0x3F
-#define GPP_E20_IRQ				0x40
-#define GPP_E21_IRQ				0x41
-#define GPP_E22_IRQ				0x42
-#define GPP_E23_IRQ				0x43
-
-/* Register defines. */
-#define GPIO_MISCCFG				0x10
-#define  GPE_DW_SHIFT				8
-#define  GPE_DW_MASK				0xfff00
-#define HOSTSW_OWN_REG_0			0xb0
-#define GPI_INT_STS_0				0x100
-#define GPI_INT_EN_0				0x110
-#define GPI_SMI_STS_0				0x180
-#define GPI_SMI_EN_0				0x1A0
-#define PAD_CFG_BASE				0x700
-
-#endif
diff --git a/src/soc/intel/jasperlake/include/soc/gpio_soc_defs.h b/src/soc/intel/jasperlake/include/soc/gpio_soc_defs.h
index b3ab9c3b5b..4570fceac8 100644
--- a/src/soc/intel/jasperlake/include/soc/gpio_soc_defs.h
+++ b/src/soc/intel/jasperlake/include/soc/gpio_soc_defs.h
@@ -11,13 +11,348 @@
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  */
-#ifndef _SOC_TIGERLAKE_GPIO_SOC_DEFS_H_
-#define _SOC_TIGERLAKE_GPIO_SOC_DEFS_H_
 
-#if CONFIG(SOC_INTEL_TIGERLAKE_COPY)
-	#include "gpio_soc_defs_tgl.h"
-#elif CONFIG(SOC_INTEL_JASPERLAKE_COPY)
-	#include "gpio_soc_defs_jsl.h"
-#endif
+#ifndef _SOC_JASPERLAKE_GPIO_SOC_DEFS_H_
+#define _SOC_JASPERLAKE_GPIO_SOC_DEFS_H_
+
+/*
+ * Most of the fixed numbers and macros are based on the GPP groups.
+ * The GPIO groups are accessed through register blocks called
+ * communities.
+ */
+
+#define GPP_A			0x0
+#define GPP_B			0x1
+#define GPP_G			0x2
+#define GPP_C			0x3
+#define GPP_R			0x4
+#define GPP_D			0x5
+#define GPP_S			0x6
+#define GPP_H			0x7
+#define GPP_VGPIO		0x8
+#define GPP_F			0x9
+#define GPP_GPD			0xA
+#define GPP_E			0xD
+
+#define GPIO_NUM_GROUPS		12
+#define GPIO_MAX_NUM_PER_GROUP	24
+
+/*
+ * GPIOs are ordered monotonically increasing to match ACPI/OS driver.
+ */
+
+/* Group F */
+#define GPP_F0		0
+#define GPP_F1		1
+#define GPP_F2		2
+#define GPP_F3		3
+#define GPP_F4		4
+#define GPP_F5		5
+#define GPP_F6		6
+#define GPP_F7		7
+#define GPP_F8		8
+#define GPP_F9		9
+#define GPP_F10		10
+#define GPP_F11		11
+#define GPP_F12		12
+#define GPP_F13		13
+#define GPP_F14		14
+#define GPP_F15		15
+#define GPP_F16		16
+#define GPP_F17		17
+#define GPP_F18		18
+#define GPP_F19		19
+
+/* Group B */
+#define GPIO_RSVD_0	20
+#define GPIO_RSVD_1	21
+#define GPIO_RSVD_2	22
+#define GPIO_RSVD_3	23
+#define GPIO_RSVD_4	24
+#define GPIO_RSVD_5	25
+#define GPIO_RSVD_6	26
+#define GPIO_RSVD_7	27
+#define GPIO_RSVD_8	28
+#define GPP_B0		29
+#define GPP_B1		30
+#define GPP_B2		31
+#define GPP_B3		32
+#define GPP_B4		33
+#define GPP_B5		34
+#define GPP_B6		35
+#define GPP_B7		36
+#define GPP_B8		37
+#define GPP_B9		38
+#define GPP_B10		39
+#define GPP_B11		40
+#define GPP_B12		41
+#define GPP_B13		42
+#define GPP_B14		43
+#define GPP_B15		44
+#define GPP_B16		45
+#define GPP_B17		46
+#define GPP_B18		47
+#define GPP_B19		48
+#define GPP_B20		49
+#define GPP_B21		50
+#define GPP_B22		51
+#define GPP_B23		52
+#define GPIO_RSVD_9	53
+#define GPIO_RSVD_10	54
+
+/* Group A */
+#define GPP_A0		55
+#define GPP_A1		56
+#define GPP_A2		57
+#define GPP_A3		58
+#define GPP_A4		59
+#define GPP_A5		60
+#define GPP_A6		61
+#define GPP_A7		62
+#define GPP_A8		63
+#define GPP_A9		64
+#define GPP_A10		65
+#define GPP_A11		66
+#define GPP_A12		67
+#define GPP_A13		68
+#define GPP_A14		69
+#define GPP_A15		70
+#define GPP_A16		71
+#define GPP_A17		72
+#define GPP_A18		73
+#define GPP_A19		74
+#define GPIO_RSVD_11	75
+
+/* Group S */
+#define GPP_S0		76
+#define GPP_S1		77
+#define GPP_S2		78
+#define GPP_S3		79
+#define GPP_S4		80
+#define GPP_S5		81
+#define GPP_S6		82
+#define GPP_S7		83
+
+/* Group R */
+#define GPP_R0		84
+#define GPP_R1		85
+#define GPP_R2		86
+#define GPP_R3		87
+#define GPP_R4		88
+#define GPP_R5		89
+#define GPP_R6		90
+#define GPP_R7		91
+
+#define GPIO_COM0_START		GPP_F0
+#define GPIO_COM0_END		GPP_R7
+#define NUM_GPIO_COM0_PADS	(GPIO_COM0_END - GPIO_COM0_START + 1)
+
+/* Group H */
+#define GPP_H0		92
+#define GPP_H1		93
+#define GPP_H2		94
+#define GPP_H3		95
+#define GPP_H4		96
+#define GPP_H5		97
+#define GPP_H6		98
+#define GPP_H7		99
+#define GPP_H8		100
+#define GPP_H9		101
+#define GPP_H10		102
+#define GPP_H11		103
+#define GPP_H12		104
+#define GPP_H13		105
+#define GPP_H14		106
+#define GPP_H15		107
+#define GPP_H16		108
+#define GPP_H17		109
+#define GPP_H18		110
+#define GPP_H19		111
+#define GPP_H20		112
+#define GPP_H21		113
+#define GPP_H22		114
+#define GPP_H23		115
+
+/* Group D */
+#define GPP_D0		116
+#define GPP_D1		117
+#define GPP_D2		118
+#define GPP_D3		119
+#define GPP_D4		120
+#define GPP_D5		121
+#define GPP_D6		122
+#define GPP_D7		123
+#define GPP_D8		124
+#define GPP_D9		125
+#define GPP_D10		126
+#define GPP_D11		127
+#define GPP_D12		128
+#define GPP_D13		129
+#define GPP_D14		130
+#define GPP_D15		131
+#define GPP_D16		132
+#define GPP_D17		133
+#define GPP_D18		134
+#define GPP_D19		135
+#define GPP_D20		136
+#define GPP_D21		137
+#define GPP_D22		138
+#define GPP_D23		139
+#define GPIO_RSVD_12	140
+#define GPIO_RSVD_13	141
+
+/* Group VGPIO */
+#define VGPIO_0		142
+#define VGPIO_3		143
+#define VGPIO_4		144
+#define VGPIO_5		145
+#define VGPIO_6		146
+#define VGPIO_7		147
+#define VGPIO_8		148
+#define VGPIO_9		149
+#define VGPIO_10	150
+#define VGPIO_11	151
+#define VGPIO_12	152
+#define VGPIO_13	153
+#define VGPIO_18	154
+#define VGPIO_19	155
+#define VGPIO_20	156
+#define VGPIO_21	157
+#define VGPIO_22	158
+#define VGPIO_23	159
+#define VGPIO_24	160
+#define VGPIO_25	161
+#define VGPIO_30	162
+#define VGPIO_31	163
+#define VGPIO_32	164
+#define VGPIO_33	165
+#define VGPIO_34	166
+#define VGPIO_35	167
+#define VGPIO_36	168
+#define VGPIO_37	169
+#define VGPIO_39	170
+
+/* Group C */
+#define GPP_C0		171
+#define GPP_C1		172
+#define GPP_C2		173
+#define GPP_C3		174
+#define GPP_C4		175
+#define GPP_C5		176
+#define GPP_C6		177
+#define GPP_C7		178
+#define GPP_C8		179
+#define GPP_C9		180
+#define GPP_C10		181
+#define GPP_C11		182
+#define GPP_C12		183
+#define GPP_C13		184
+#define GPP_C14		185
+#define GPP_C15		186
+#define GPP_C16		187
+#define GPP_C17		188
+#define GPP_C18		189
+#define GPP_C19		190
+#define GPP_C20		191
+#define GPP_C21		192
+#define GPP_C22		193
+#define GPP_C23		194
+
+#define GPIO_COM1_START		GPP_H0
+#define GPIO_COM1_END		GPP_C23
+#define NUM_GPIO_COM1_PADS	(GPIO_COM1_END - GPIO_COM1_START + 1)
+
+/* Group GPD */
+#define GPD0		195
+#define GPD1		196
+#define GPD2		197
+#define GPD3		198
+#define GPD4		199
+#define GPD5		200
+#define GPD6		201
+#define GPD7		202
+#define GPD8		203
+#define GPD9		204
+#define GPD10		205
+#define GPIO_RSVD_14	206
+#define GPIO_RSVD_15	207
+#define GPIO_RSVD_16	208
+#define GPIO_RSVD_17	209
+
+#define GPIO_COM2_START		GPD0
+#define GPIO_COM2_END		GPIO_RSVD_17
+#define NUM_GPIO_COM2_PADS	(GPIO_COM2_END - GPIO_COM2_START + 1)
+
+/* Group E */
+#define GPIO_RSVD_18	210
+#define GPIO_RSVD_19	211
+#define GPIO_RSVD_20	212
+#define GPIO_RSVD_21	213
+#define GPIO_RSVD_22	214
+#define GPIO_RSVD_23	215
+#define GPP_E0		216
+#define GPP_E1		217
+#define GPP_E2		218
+#define GPP_E3		219
+#define GPP_E4		220
+#define GPP_E5		221
+#define GPP_E6		222
+#define GPP_E7		223
+#define GPP_E8		224
+#define GPP_E9		225
+#define GPP_E10		226
+#define GPP_E11		227
+#define GPP_E12		228
+#define GPP_E13		229
+#define GPP_E14		230
+#define GPP_E15		231
+#define GPP_E16		232
+#define GPP_E17		233
+#define GPP_E18		234
+#define GPP_E19		235
+#define GPP_E20		236
+#define GPP_E21		237
+#define GPP_E22		238
+#define GPP_E23		239
+#define GPIO_RSVD_24	240
+#define GPIO_RSVD_25	241
+#define GPIO_RSVD_26	242
+#define GPIO_RSVD_27	243
+#define GPIO_RSVD_28	244
+#define GPIO_RSVD_29	245
+#define GPIO_RSVD_30	246
+#define GPIO_RSVD_31	247
+#define GPIO_RSVD_32	248
+#define GPIO_RSVD_33	249
+#define GPIO_RSVD_34	250
+#define GPIO_RSVD_35	251
+#define GPIO_RSVD_36	252
+
+#define GPIO_COM4_START		GPIO_RSVD_18
+#define GPIO_COM4_END		GPIO_RSVD_36
+#define NUM_GPIO_COM4_PADS	(GPIO_COM4_END - GPIO_COM4_START + 1)
+
+/* Group G */
+#define GPP_G0		253
+#define GPP_G1		254
+#define GPP_G2		255
+#define GPP_G3		256
+#define GPP_G4		257
+#define GPP_G5		258
+#define GPP_G6		259
+#define GPP_G7		260
+
+#define GPIO_COM5_START		GPP_G0
+#define GPIO_COM5_END		GPP_G7
+#define NUM_GPIO_COM5_PADS	(GPIO_COM5_END - GPIO_COM5_START + 1)
+
+#define TOTAL_PADS	261
+
+#define COMM_0		0
+#define COMM_1		1
+#define COMM_2		2
+#define COMM_4		3
+#define COMM_5		4
+#define TOTAL_GPIO_COMM	5
 
 #endif
diff --git a/src/soc/intel/jasperlake/include/soc/gpio_soc_defs_jsl.h b/src/soc/intel/jasperlake/include/soc/gpio_soc_defs_jsl.h
deleted file mode 100644
index 2ee52b260f..0000000000
--- a/src/soc/intel/jasperlake/include/soc/gpio_soc_defs_jsl.h
+++ /dev/null
@@ -1,358 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef _SOC_JASPERLAKE_GPIO_SOC_DEFS_JSL_H_
-#define _SOC_JASPERLAKE_GPIO_SOC_DEFS_JSL_H_
-
-/*
- * Most of the fixed numbers and macros are based on the GPP groups.
- * The GPIO groups are accessed through register blocks called
- * communities.
- */
-
-#define GPP_A			0x0
-#define GPP_B			0x1
-#define GPP_G			0x2
-#define GPP_C			0x3
-#define GPP_R			0x4
-#define GPP_D			0x5
-#define GPP_S			0x6
-#define GPP_H			0x7
-#define GPP_VGPIO		0x8
-#define GPP_F			0x9
-#define GPP_GPD			0xA
-#define GPP_E			0xD
-
-#define GPIO_NUM_GROUPS		12
-#define GPIO_MAX_NUM_PER_GROUP	24
-
-/*
- * GPIOs are ordered monotonically increasing to match ACPI/OS driver.
- */
-
-/* Group F */
-#define GPP_F0		0
-#define GPP_F1		1
-#define GPP_F2		2
-#define GPP_F3		3
-#define GPP_F4		4
-#define GPP_F5		5
-#define GPP_F6		6
-#define GPP_F7		7
-#define GPP_F8		8
-#define GPP_F9		9
-#define GPP_F10		10
-#define GPP_F11		11
-#define GPP_F12		12
-#define GPP_F13		13
-#define GPP_F14		14
-#define GPP_F15		15
-#define GPP_F16		16
-#define GPP_F17		17
-#define GPP_F18		18
-#define GPP_F19		19
-
-/* Group B */
-#define GPIO_RSVD_0	20
-#define GPIO_RSVD_1	21
-#define GPIO_RSVD_2	22
-#define GPIO_RSVD_3	23
-#define GPIO_RSVD_4	24
-#define GPIO_RSVD_5	25
-#define GPIO_RSVD_6	26
-#define GPIO_RSVD_7	27
-#define GPIO_RSVD_8	28
-#define GPP_B0		29
-#define GPP_B1		30
-#define GPP_B2		31
-#define GPP_B3		32
-#define GPP_B4		33
-#define GPP_B5		34
-#define GPP_B6		35
-#define GPP_B7		36
-#define GPP_B8		37
-#define GPP_B9		38
-#define GPP_B10		39
-#define GPP_B11		40
-#define GPP_B12		41
-#define GPP_B13		42
-#define GPP_B14		43
-#define GPP_B15		44
-#define GPP_B16		45
-#define GPP_B17		46
-#define GPP_B18		47
-#define GPP_B19		48
-#define GPP_B20		49
-#define GPP_B21		50
-#define GPP_B22		51
-#define GPP_B23		52
-#define GPIO_RSVD_9	53
-#define GPIO_RSVD_10	54
-
-/* Group A */
-#define GPP_A0		55
-#define GPP_A1		56
-#define GPP_A2		57
-#define GPP_A3		58
-#define GPP_A4		59
-#define GPP_A5		60
-#define GPP_A6		61
-#define GPP_A7		62
-#define GPP_A8		63
-#define GPP_A9		64
-#define GPP_A10		65
-#define GPP_A11		66
-#define GPP_A12		67
-#define GPP_A13		68
-#define GPP_A14		69
-#define GPP_A15		70
-#define GPP_A16		71
-#define GPP_A17		72
-#define GPP_A18		73
-#define GPP_A19		74
-#define GPIO_RSVD_11	75
-
-/* Group S */
-#define GPP_S0		76
-#define GPP_S1		77
-#define GPP_S2		78
-#define GPP_S3		79
-#define GPP_S4		80
-#define GPP_S5		81
-#define GPP_S6		82
-#define GPP_S7		83
-
-/* Group R */
-#define GPP_R0		84
-#define GPP_R1		85
-#define GPP_R2		86
-#define GPP_R3		87
-#define GPP_R4		88
-#define GPP_R5		89
-#define GPP_R6		90
-#define GPP_R7		91
-
-#define GPIO_COM0_START		GPP_F0
-#define GPIO_COM0_END		GPP_R7
-#define NUM_GPIO_COM0_PADS	(GPIO_COM0_END - GPIO_COM0_START + 1)
-
-/* Group H */
-#define GPP_H0		92
-#define GPP_H1		93
-#define GPP_H2		94
-#define GPP_H3		95
-#define GPP_H4		96
-#define GPP_H5		97
-#define GPP_H6		98
-#define GPP_H7		99
-#define GPP_H8		100
-#define GPP_H9		101
-#define GPP_H10		102
-#define GPP_H11		103
-#define GPP_H12		104
-#define GPP_H13		105
-#define GPP_H14		106
-#define GPP_H15		107
-#define GPP_H16		108
-#define GPP_H17		109
-#define GPP_H18		110
-#define GPP_H19		111
-#define GPP_H20		112
-#define GPP_H21		113
-#define GPP_H22		114
-#define GPP_H23		115
-
-/* Group D */
-#define GPP_D0		116
-#define GPP_D1		117
-#define GPP_D2		118
-#define GPP_D3		119
-#define GPP_D4		120
-#define GPP_D5		121
-#define GPP_D6		122
-#define GPP_D7		123
-#define GPP_D8		124
-#define GPP_D9		125
-#define GPP_D10		126
-#define GPP_D11		127
-#define GPP_D12		128
-#define GPP_D13		129
-#define GPP_D14		130
-#define GPP_D15		131
-#define GPP_D16		132
-#define GPP_D17		133
-#define GPP_D18		134
-#define GPP_D19		135
-#define GPP_D20		136
-#define GPP_D21		137
-#define GPP_D22		138
-#define GPP_D23		139
-#define GPIO_RSVD_12	140
-#define GPIO_RSVD_13	141
-
-/* Group VGPIO */
-#define VGPIO_0		142
-#define VGPIO_3		143
-#define VGPIO_4		144
-#define VGPIO_5		145
-#define VGPIO_6		146
-#define VGPIO_7		147
-#define VGPIO_8		148
-#define VGPIO_9		149
-#define VGPIO_10	150
-#define VGPIO_11	151
-#define VGPIO_12	152
-#define VGPIO_13	153
-#define VGPIO_18	154
-#define VGPIO_19	155
-#define VGPIO_20	156
-#define VGPIO_21	157
-#define VGPIO_22	158
-#define VGPIO_23	159
-#define VGPIO_24	160
-#define VGPIO_25	161
-#define VGPIO_30	162
-#define VGPIO_31	163
-#define VGPIO_32	164
-#define VGPIO_33	165
-#define VGPIO_34	166
-#define VGPIO_35	167
-#define VGPIO_36	168
-#define VGPIO_37	169
-#define VGPIO_39	170
-
-/* Group C */
-#define GPP_C0		171
-#define GPP_C1		172
-#define GPP_C2		173
-#define GPP_C3		174
-#define GPP_C4		175
-#define GPP_C5		176
-#define GPP_C6		177
-#define GPP_C7		178
-#define GPP_C8		179
-#define GPP_C9		180
-#define GPP_C10		181
-#define GPP_C11		182
-#define GPP_C12		183
-#define GPP_C13		184
-#define GPP_C14		185
-#define GPP_C15		186
-#define GPP_C16		187
-#define GPP_C17		188
-#define GPP_C18		189
-#define GPP_C19		190
-#define GPP_C20		191
-#define GPP_C21		192
-#define GPP_C22		193
-#define GPP_C23		194
-
-#define GPIO_COM1_START		GPP_H0
-#define GPIO_COM1_END		GPP_C23
-#define NUM_GPIO_COM1_PADS	(GPIO_COM1_END - GPIO_COM1_START + 1)
-
-/* Group GPD */
-#define GPD0		195
-#define GPD1		196
-#define GPD2		197
-#define GPD3		198
-#define GPD4		199
-#define GPD5		200
-#define GPD6		201
-#define GPD7		202
-#define GPD8		203
-#define GPD9		204
-#define GPD10		205
-#define GPIO_RSVD_14	206
-#define GPIO_RSVD_15	207
-#define GPIO_RSVD_16	208
-#define GPIO_RSVD_17	209
-
-#define GPIO_COM2_START		GPD0
-#define GPIO_COM2_END		GPIO_RSVD_17
-#define NUM_GPIO_COM2_PADS	(GPIO_COM2_END - GPIO_COM2_START + 1)
-
-/* Group E */
-#define GPIO_RSVD_18	210
-#define GPIO_RSVD_19	211
-#define GPIO_RSVD_20	212
-#define GPIO_RSVD_21	213
-#define GPIO_RSVD_22	214
-#define GPIO_RSVD_23	215
-#define GPP_E0		216
-#define GPP_E1		217
-#define GPP_E2		218
-#define GPP_E3		219
-#define GPP_E4		220
-#define GPP_E5		221
-#define GPP_E6		222
-#define GPP_E7		223
-#define GPP_E8		224
-#define GPP_E9		225
-#define GPP_E10		226
-#define GPP_E11		227
-#define GPP_E12		228
-#define GPP_E13		229
-#define GPP_E14		230
-#define GPP_E15		231
-#define GPP_E16		232
-#define GPP_E17		233
-#define GPP_E18		234
-#define GPP_E19		235
-#define GPP_E20		236
-#define GPP_E21		237
-#define GPP_E22		238
-#define GPP_E23		239
-#define GPIO_RSVD_24	240
-#define GPIO_RSVD_25	241
-#define GPIO_RSVD_26	242
-#define GPIO_RSVD_27	243
-#define GPIO_RSVD_28	244
-#define GPIO_RSVD_29	245
-#define GPIO_RSVD_30	246
-#define GPIO_RSVD_31	247
-#define GPIO_RSVD_32	248
-#define GPIO_RSVD_33	249
-#define GPIO_RSVD_34	250
-#define GPIO_RSVD_35	251
-#define GPIO_RSVD_36	252
-
-#define GPIO_COM4_START		GPIO_RSVD_18
-#define GPIO_COM4_END		GPIO_RSVD_36
-#define NUM_GPIO_COM4_PADS	(GPIO_COM4_END - GPIO_COM4_START + 1)
-
-/* Group G */
-#define GPP_G0		253
-#define GPP_G1		254
-#define GPP_G2		255
-#define GPP_G3		256
-#define GPP_G4		257
-#define GPP_G5		258
-#define GPP_G6		259
-#define GPP_G7		260
-
-#define GPIO_COM5_START		GPP_G0
-#define GPIO_COM5_END		GPP_G7
-#define NUM_GPIO_COM5_PADS	(GPIO_COM5_END - GPIO_COM5_START + 1)
-
-#define TOTAL_PADS	261
-
-#define COMM_0		0
-#define COMM_1		1
-#define COMM_2		2
-#define COMM_4		3
-#define COMM_5		4
-#define TOTAL_GPIO_COMM	5
-
-#endif
diff --git a/src/soc/intel/jasperlake/include/soc/gpio_soc_defs_tgl.h b/src/soc/intel/jasperlake/include/soc/gpio_soc_defs_tgl.h
deleted file mode 100644
index ec582c3133..0000000000
--- a/src/soc/intel/jasperlake/include/soc/gpio_soc_defs_tgl.h
+++ /dev/null
@@ -1,394 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#ifndef _SOC_TIGERLAKE_GPIO_SOC_DEFS_TGL_H_
-#define _SOC_TIGERLAKE_GPIO_SOC_DEFS_TGL_H_
-/*
- * Most of the fixed numbers and macros are based on the GPP groups.
- * The GPIO groups are accessed through register blocks called
- * communities.
- */
-#define GPP_B			0x0
-#define GPP_T			0x1
-#define GPP_A			0x2
-#define GPP_R			0x3
-#define GPD			0x4
-#define GPP_S			0x5
-#define GPP_H			0x6
-#define GPP_D			0x7
-#define GPP_U			0x8
-#define GPP_F			0xA
-#define GPP_C			0xB
-#define GPP_E			0xC
-
-#define GPIO_MAX_NUM_PER_GROUP	27
-
-#define COMM_0			0
-#define COMM_1			1
-#define COMM_2			2
-/* GPIO community 3 is not exposed to be used and hence is skipped. */
-#define COMM_4			3
-#define COMM_5			4
-/*
- * GPIOs are ordered monotonically increasing to match ACPI/OS driver.
- */
-/* Group B */
-#define GPP_B0			0
-#define GPP_B1			1
-#define GPP_B2			2
-#define GPP_B3			3
-#define GPP_B4			4
-#define GPP_B5			5
-#define GPP_B6			6
-#define GPP_B7			7
-#define GPP_B8			8
-#define GPP_B9			9
-#define GPP_B10			10
-#define GPP_B11			11
-#define GPP_B12			12
-#define GPP_B13			13
-#define GPP_B14			14
-#define GPP_B15			15
-#define GPP_B16			16
-#define GPP_B17			17
-#define GPP_B18			18
-#define GPP_B19			19
-#define GPP_B20			20
-#define GPP_B21			21
-#define GPP_B22			22
-#define GPP_B23			23
-#define GPP_B24			24 /* GSPI0_CLK_LOOPBK */
-#define GPP_B25			25 /* GSPI1_CLK_LOOPBK */
-
-/* Group T */
-#define GPP_T0			26
-#define GPP_T1			27
-#define GPP_T2			28
-#define GPP_T3			29
-#define GPP_T4			30
-#define GPP_T5			31
-#define GPP_T6			32
-#define GPP_T7			33
-#define GPP_T8			34
-#define GPP_T9			35
-#define GPP_T10			36
-#define GPP_T11			37
-#define GPP_T12			38
-#define GPP_T13			39
-#define GPP_T14			40
-#define GPP_T15			41
-
-/* Group A */
-#define GPP_A0			42
-#define GPP_A1			43
-#define GPP_A2			44
-#define GPP_A3			45
-#define GPP_A4			46
-#define GPP_A5			47
-#define GPP_A6			48
-#define GPP_A7			49
-#define GPP_A8			50
-#define GPP_A9			51
-#define GPP_A10			52
-#define GPP_A11			53
-#define GPP_A12			54
-#define GPP_A13			55
-#define GPP_A14			56
-#define GPP_A15			57
-#define GPP_A16			58
-#define GPP_A17			59
-#define GPP_A18			60
-#define GPP_A19			61
-#define GPP_A20			62
-#define GPP_A21			63
-#define GPP_A22			64
-#define GPP_A23			65
-#define GPP_A24			66 /* ESPI_CLK_LOOPBK */
-
-#define GPIO_COM0_START		GPP_B0
-#define GPIO_COM0_END		GPP_A24
-#define NUM_GPIO_COM0_PADS	(GPP_A24 - GPP_B0 + 1)
-
-/* Group S */
-#define GPP_S0			67
-#define GPP_S1			68
-#define GPP_S2			69
-#define GPP_S3			70
-#define GPP_S4			71
-#define GPP_S5			72
-#define GPP_S6			73
-#define GPP_S7			74
-
-/* Group H */
-#define GPP_H0			75
-#define GPP_H1			76
-#define GPP_H2			77
-#define GPP_H3			78
-#define GPP_H4			79
-#define GPP_H5			80
-#define GPP_H6			81
-#define GPP_H7			82
-#define GPP_H8			83
-#define GPP_H9			84
-#define GPP_H10			85
-#define GPP_H11			86
-#define GPP_H12			87
-#define GPP_H13			88
-#define GPP_H14			89
-#define GPP_H15			90
-#define GPP_H16			91
-#define GPP_H17			92
-#define GPP_H18			93
-#define GPP_H19			94
-#define GPP_H20			95
-#define GPP_H21			96
-#define GPP_H22			97
-#define GPP_H23			98
-
-/* Group D */
-#define GPP_D0			99
-#define GPP_D1			100
-#define GPP_D2			101
-#define GPP_D3			102
-#define GPP_D4			103
-#define GPP_D5			104
-#define GPP_D6			105
-#define GPP_D7			106
-#define GPP_D8			107
-#define GPP_D9			108
-#define GPP_D10			109
-#define GPP_D11			110
-#define GPP_D12			111
-#define GPP_D13			112
-#define GPP_D14			113
-#define GPP_D15			114
-#define GPP_D16			115
-#define GPP_D17			116
-#define GPP_D18			117
-#define GPP_D19			118
-#define GPP_GSPI2_CLK_LOOPBK	119
-
-/* Group U */
-#define GPP_U0			120
-#define GPP_U1			121
-#define GPP_U2			122
-#define GPP_U3			123
-#define GPP_U4			124
-#define GPP_U5			125
-#define GPP_U6			126
-#define GPP_U7			127
-#define GPP_U8			128
-#define GPP_U9			129
-#define GPP_U10			130
-#define GPP_U11			131
-#define GPP_U12			132
-#define GPP_U13			133
-#define GPP_U14			134
-#define GPP_U15			135
-#define GPP_U16			136
-#define GPP_U17			137
-#define GPP_U18			138
-#define GPP_U19			139
-#define GPP_GSPI3_CLK_LOOPBK	140
-#define GPP_GSPI4_CLK_LOOPBK	141
-#define GPP_GSPI5_CLK_LOOPBK	142
-#define GPP_GSPI6_CLK_LOOPBK	143
-
-/* Group VGPIO */
-#define CNV_BTEN		144
-#define CNV_BT_HOST_WAKEB	145
-#define CNV_BT_IF_SELECT	146
-#define vCNV_BT_UART_TXD	147
-#define vCNV_BT_UART_RXD	148
-#define vCNV_BT_UART_CTS_B	149
-#define vCNV_BT_UART_RTS_B	150
-#define vCNV_MFUART1_TXD	151
-#define vCNV_MFUART1_RXD	152
-#define vCNV_MFUART1_CTS_B	153
-#define vCNV_MFUART1_RTS_B	154
-#define vUART0_TXD		155
-#define vUART0_RXD		156
-#define vUART0_CTS_B		157
-#define vUART0_RTS_B		158
-#define vISH_UART0_TXD		159
-#define vISH_UART0_RXD		160
-#define vISH_UART0_CTS_B	161
-#define vISH_UART0_RTS_B	162
-#define vCNV_BT_I2S_BCLK	163
-#define vCNV_BT_I2S_WS_SYNC	164
-#define vCNV_BT_I2S_SDO		165
-#define vCNV_BT_I2S_SDI		166
-#define vI2S2_SCLK		167
-#define vI2S2_SFRM		168
-#define vI2S2_TXD		169
-#define vI2S2_RXD		170
-
-#define GPIO_COM1_START		GPP_S0
-#define GPIO_COM1_END		vI2S2_RXD
-#define NUM_GPIO_COM1_PADS	(vI2S2_RXD - GPP_S0 + 1)
-
-/* Group GPD  */
-#define GPD0			171
-#define GPD1			172
-#define GPD2			173
-#define GPD3			174
-#define GPD4			175
-#define GPD5			176
-#define GPD6			177
-#define GPD7			178
-#define GPD8			179
-#define GPD9			180
-#define GPD10			181
-#define GPD11			182
-#define GPD_INPUT3VSEL		183
-#define GPD_SLP_LANB		184
-#define GPD__SLP_SUSB		185
-#define GPD_WAKEB		186
-#define GPD_DRAM_RESETB		187
-
-#define GPIO_COM2_START		GPD0
-#define GPIO_COM2_END		GPD_DRAM_RESETB
-#define NUM_GPIO_COM2_PADS	(GPD_DRAM_RESETB - GPD0 + 1)
-
-/* Group C */
-#define GPP_C0			188
-#define GPP_C1			189
-#define GPP_C2			190
-#define GPP_C3			191
-#define GPP_C4			192
-#define GPP_C5			193
-#define GPP_C6			194
-#define GPP_C7			195
-#define GPP_C8			196
-#define GPP_C9			197
-#define GPP_C10			198
-#define GPP_C11			199
-#define GPP_C12			200
-#define GPP_C13			201
-#define GPP_C14			202
-#define GPP_C15			203
-#define GPP_C16			204
-#define GPP_C17			205
-#define GPP_C18			206
-#define GPP_C19			207
-#define GPP_C20			208
-#define GPP_C21			209
-#define GPP_C22			210
-#define GPP_C23			211
-
-/* Group F */
-#define GPP_F0			212
-#define GPP_F1			213
-#define GPP_F2			214
-#define GPP_F3			215
-#define GPP_F4			216
-#define GPP_F5			217
-#define GPP_F6			218
-#define GPP_F7			219
-#define GPP_F8			220
-#define GPP_F9			221
-#define GPP_F10			222
-#define GPP_F11			223
-#define GPP_F12			224
-#define GPP_F13			225
-#define GPP_F14			226
-#define GPP_F15			227
-#define GPP_F16			228
-#define GPP_F17			229
-#define GPP_F18			230
-#define GPP_F19			231
-#define GPP_F20			232
-#define GPP_F21			233
-#define GPP_F22			234
-#define GPP_F23			235
-#define GPP_F_CLK_LOOPBK        236
-
-/* Group HVCMOS */
-#define GPP_L_BKLTEN		237
-#define GPP_L_BKLTCTL		238
-#define GPP_L_VDDEN		239
-#define GPP_SYS_PWROK		240
-#define GPP_SYS_RESETB		241
-#define GPP_MLK_RSTB		242
-
-/* Group E */
-#define GPP_E0			243
-#define GPP_E1			244
-#define GPP_E2			245
-#define GPP_E3			246
-#define GPP_E4			247
-#define GPP_E5			248
-#define GPP_E6			249
-#define GPP_E7			250
-#define GPP_E8			251
-#define GPP_E9			252
-#define GPP_E10			253
-#define GPP_E11			254
-#define GPP_E12			255
-#define GPP_E13			256
-#define GPP_E14			257
-#define GPP_E15			258
-#define GPP_E16			259
-#define GPP_E17			260
-#define GPP_E18			261
-#define GPP_E19			262
-#define GPP_E20			263
-#define GPP_E21			264
-#define GPP_E22			265
-#define GPP_E23			266
-#define GPP_E_CLK_LOOPBK	267
-
-/* Group JTAG */
-#define GPP_JTAG_TDO		268
-#define GPP_JTAG_X		269
-#define GPP_JTAG_PRDYB		270
-#define GPP_JTAG_PREQB		271
-#define GPP_CPU_TRSTB		272
-#define GPP_JTAG_TDI		273
-#define GPP_JTAG_TMS		274
-#define GPP_JTAG_TCK		275
-#define GPP_DBG_PMODE		276
-
-#define GPIO_COM4_START		GPP_C0
-#define GPIO_COM4_END		GPP_DBG_PMODE
-#define NUM_GPIO_COM4_PADS	(GPP_DBG_PMODE - GPP_C0 + 1)
-
-/* Group R */
-#define GPP_R0			277
-#define GPP_R1			278
-#define GPP_R2			279
-#define GPP_R3			280
-#define GPP_R4			281
-#define GPP_R5			282
-#define GPP_R6			283
-#define GPP_R7			284
-
-/* Group SPI */
-#define GPP_SPI_IO_2		285
-#define GPP_SPI_IO_3		286
-#define GPP_SPI_MOSI_IO_0	287
-#define GPP_SPI_MOSI_IO_1	288
-#define GPP_SPI_TPM_CSB		289
-#define GPP_SPI_FLASH_0_CSB	290
-#define GPP_SPI_FLASH_1_CSB	291
-#define GPP_SPI_CLK		292
-#define GPP_CLK_LOOPBK		293
-
-#define GPIO_COM5_START		GPP_R0
-#define GPIO_COM5_END		GPP_CLK_LOOPBK
-#define NUM_GPIO_COM5_PADS	(GPP_CLK_LOOPBK - GPP_R0 + 1)
-
-#define TOTAL_GPIO_COMM		(COMM_5 + 1)
-#define TOTAL_PADS		294
-
-#endif
diff --git a/src/soc/intel/jasperlake/include/soc/iomap.h b/src/soc/intel/jasperlake/include/soc/iomap.h
index 5eda08a132..ef166382ac 100644
--- a/src/soc/intel/jasperlake/include/soc/iomap.h
+++ b/src/soc/intel/jasperlake/include/soc/iomap.h
@@ -12,14 +12,8 @@
  * GNU General Public License for more details.
  */
 
-/*
- * This file is created based on Intel Tiger Lake Firmware Architecture Specification
- * Document number: 608531
- * Chapter number: 4
- */
-
-#ifndef _SOC_TIGERLAKE_IOMAP_H_
-#define _SOC_TIGERLAKE_IOMAP_H_
+#ifndef _SOC_JASPERLAKE_IOMAP_H_
+#define _SOC_JASPERLAKE_IOMAP_H_
 
 /*
  * Memory-mapped I/O registers.
@@ -91,18 +85,6 @@
 #define ABOVE_4GB_MEM_BASE_ADDRESS	(256ULL * GiB)
 #define ABOVE_4GB_MEM_BASE_SIZE	(256ULL * GiB)
 
-#if CONFIG(SOC_INTEL_TIGERLAKE_COPY)
-
-#define MCH_BASE_ADDRESS	0xfedc0000
-#define MCH_BASE_SIZE		0x20000
-
-#define EARLY_GSPI_BASE_ADDRESS 0xfe030000
-
-#define EARLY_I2C_BASE_ADDRESS	0xfe020000
-#define EARLY_I2C_BASE(x)	(EARLY_I2C_BASE_ADDRESS + (0x2000 * (x)))
-
-#else /* CONFIG_SOC_INTEL_JASPERLAKE_COPY */
-
 #define MCH_BASE_ADDRESS	0xfea80000
 #define MCH_BASE_SIZE		0x8000
 
@@ -111,8 +93,6 @@
 #define EARLY_I2C_BASE_ADDRESS	0xfe040000
 #define EARLY_I2C_BASE(x)	(EARLY_I2C_BASE_ADDRESS + (0x1000 * (x)))
 
-#endif
-
 /*
  * I/O port address space
  */
diff --git a/src/soc/intel/jasperlake/include/soc/irq.h b/src/soc/intel/jasperlake/include/soc/irq.h
index 6ca2588a0d..a6edd23d97 100644
--- a/src/soc/intel/jasperlake/include/soc/irq.h
+++ b/src/soc/intel/jasperlake/include/soc/irq.h
@@ -12,13 +12,75 @@
  * GNU General Public License for more details.
  */
 
-#ifndef _SOC_IRQ_H_
-#define _SOC_IRQ_H_
+#ifndef _SOC_JSL_IRQ_H_
+#define _SOC_JSL_IRQ_H_
 
-#if CONFIG(SOC_INTEL_TIGERLAKE_COPY)
-	#include "irq_tgl.h"
-#else
-	#include "irq_jsl.h"
-#endif /* CONFIG_SOC_INTEL_TIGERLAKE_COPY */
+#define GPIO_IRQ14 14
+#define GPIO_IRQ15 15
 
-#endif /* _SOC_IRQ_H_ */
+#define PCH_IRQ10 10
+#define PCH_IRQ11 11
+
+/* LPSS Devices */
+#define LPSS_I2C0_IRQ 16
+#define LPSS_I2C1_IRQ 17
+#define LPSS_I2C2_IRQ 18
+#define LPSS_I2C3_IRQ 19
+#define LPSS_I2C4_IRQ 32
+#define LPSS_I2C5_IRQ 33
+#define LPSS_SPI0_IRQ 22
+#define LPSS_SPI1_IRQ 23
+#define LPSS_SPI2_IRQ 24
+#define LPSS_UART0_IRQ 20
+#define LPSS_UART1_IRQ 21
+#define LPSS_UART2_IRQ 34
+
+/* PCI D:31 F:x */
+#define cAVS_INTA_IRQ 16
+#define SMBUS_INTA_IRQ 16
+#define SMBUS_INTB_IRQ 17
+#define GbE_INTA_IRQ 16
+#define GbE_INTC_IRQ 18
+#define TRACE_HUB_INTA_IRQ 16
+#define TRACE_HUB_INTD_IRQ 19
+
+/* PCI D:28 F:x */
+#define PCIE_1_IRQ 16
+#define PCIE_2_IRQ 17
+#define PCIE_3_IRQ 18
+#define PCIE_4_IRQ 19
+#define PCIE_5_IRQ 16
+#define PCIE_6_IRQ 17
+#define PCIE_7_IRQ 18
+#define PCIE_8_IRQ 19
+
+/* PCI D:26 F:x */
+#define eMMC_IRQ 16
+
+/* PCI D:23 F:x */
+#define SATA_IRQ 16
+
+/* PCI D:22 F:x */
+#define HECI_1_IRQ 16
+#define HECI_2_IRQ 17
+#define HECI_3_IRQ 16
+#define HECI_4_IRQ 19
+#define IDER_IRQ 18
+#define KT_IRQ 19
+
+/* PCI D:20 F:x */
+#define XHCI_IRQ 16
+#define OTG_IRQ 17
+#define CNViWIFI_IRQ 16
+#define SD_IRQ 19
+#define PMC_SRAM_IRQ 18
+
+/* PCI D:18 F:x */
+#define UFS_IRQ 16
+
+#define IGFX_IRQ 16
+#define SA_THERMAL_IRQ 16
+#define IPU_IRQ 16
+#define GNA_IRQ 16
+
+#endif /* _JSL_IRQ_H_ */
diff --git a/src/soc/intel/jasperlake/include/soc/irq_jsl.h b/src/soc/intel/jasperlake/include/soc/irq_jsl.h
deleted file mode 100644
index a6edd23d97..0000000000
--- a/src/soc/intel/jasperlake/include/soc/irq_jsl.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef _SOC_JSL_IRQ_H_
-#define _SOC_JSL_IRQ_H_
-
-#define GPIO_IRQ14 14
-#define GPIO_IRQ15 15
-
-#define PCH_IRQ10 10
-#define PCH_IRQ11 11
-
-/* LPSS Devices */
-#define LPSS_I2C0_IRQ 16
-#define LPSS_I2C1_IRQ 17
-#define LPSS_I2C2_IRQ 18
-#define LPSS_I2C3_IRQ 19
-#define LPSS_I2C4_IRQ 32
-#define LPSS_I2C5_IRQ 33
-#define LPSS_SPI0_IRQ 22
-#define LPSS_SPI1_IRQ 23
-#define LPSS_SPI2_IRQ 24
-#define LPSS_UART0_IRQ 20
-#define LPSS_UART1_IRQ 21
-#define LPSS_UART2_IRQ 34
-
-/* PCI D:31 F:x */
-#define cAVS_INTA_IRQ 16
-#define SMBUS_INTA_IRQ 16
-#define SMBUS_INTB_IRQ 17
-#define GbE_INTA_IRQ 16
-#define GbE_INTC_IRQ 18
-#define TRACE_HUB_INTA_IRQ 16
-#define TRACE_HUB_INTD_IRQ 19
-
-/* PCI D:28 F:x */
-#define PCIE_1_IRQ 16
-#define PCIE_2_IRQ 17
-#define PCIE_3_IRQ 18
-#define PCIE_4_IRQ 19
-#define PCIE_5_IRQ 16
-#define PCIE_6_IRQ 17
-#define PCIE_7_IRQ 18
-#define PCIE_8_IRQ 19
-
-/* PCI D:26 F:x */
-#define eMMC_IRQ 16
-
-/* PCI D:23 F:x */
-#define SATA_IRQ 16
-
-/* PCI D:22 F:x */
-#define HECI_1_IRQ 16
-#define HECI_2_IRQ 17
-#define HECI_3_IRQ 16
-#define HECI_4_IRQ 19
-#define IDER_IRQ 18
-#define KT_IRQ 19
-
-/* PCI D:20 F:x */
-#define XHCI_IRQ 16
-#define OTG_IRQ 17
-#define CNViWIFI_IRQ 16
-#define SD_IRQ 19
-#define PMC_SRAM_IRQ 18
-
-/* PCI D:18 F:x */
-#define UFS_IRQ 16
-
-#define IGFX_IRQ 16
-#define SA_THERMAL_IRQ 16
-#define IPU_IRQ 16
-#define GNA_IRQ 16
-
-#endif /* _JSL_IRQ_H_ */
diff --git a/src/soc/intel/jasperlake/include/soc/irq_tgl.h b/src/soc/intel/jasperlake/include/soc/irq_tgl.h
deleted file mode 100644
index 6f268c1eae..0000000000
--- a/src/soc/intel/jasperlake/include/soc/irq_tgl.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef _SOC_TGL_IRQ_H_
-#define _SOC_TGL_IRQ_H_
-
-#define GPIO_IRQ14	14
-#define GPIO_IRQ15	15
-
-#define PCH_IRQ10	10
-#define PCH_IRQ11	11
-
-#define LPSS_I2C0_IRQ	27
-#define LPSS_I2C1_IRQ	28
-#define LPSS_I2C2_IRQ	29
-#define LPSS_I2C3_IRQ	30
-#define LPSS_I2C4_IRQ	31
-#define LPSS_I2C5_IRQ	32
-#define LPSS_SPI0_IRQ	36
-#define LPSS_SPI1_IRQ	37
-#define LPSS_SPI2_IRQ	18
-#define LPSS_SPI3_IRQ	23
-#define LPSS_UART0_IRQ	34
-#define LPSS_UART1_IRQ	35
-#define LPSS_UART2_IRQ	33
-
-#define HDA_IRQ		16
-#define SMBUS_IRQ	16
-#define TRACEHUB_IRQ	16
-
-#define PCIE_1_IRQ	16
-#define PCIE_2_IRQ	17
-#define PCIE_3_IRQ	18
-#define PCIE_4_IRQ	19
-#define PCIE_5_IRQ	16
-#define PCIE_6_IRQ	17
-#define PCIE_7_IRQ	18
-#define PCIE_8_IRQ	19
-#define PCIE_9_IRQ	16
-#define PCIE_10_IRQ	17
-#define PCIE_11_IRQ	18
-#define PCIE_12_IRQ	19
-
-#define SATA_IRQ	16
-
-#define xHCI_IRQ	16
-#define xDCI_IRQ	17
-#define CNVI_WIFI_IRQ	16
-
-#define CNVI_BT_IRQ	18
-
-#define THC0_IRQ	16
-#define THC1_IRQ	17
-
-#define ISH_IRQ		16
-
-#define TBT_PCIe0_IRQ	16
-#define TBT_PCIe1_IRQ	17
-#define TBT_PCIe2_IRQ	18
-#define TBT_PCIe3_IRQ	19
-
-#define HECI_1_IRQ	16
-#define HECI_2_IRQ	17
-#define HECI_3_IRQ	16
-#define HECI_4_IRQ	19
-
-#define PEG_IRQ		16
-#define IGFX_IRQ	16
-#define THERMAL_IRQ	16
-#define IPU_IRQ		16
-#define GNA_IRQ		16
-#endif /* _TGL_IRQ_H_ */
diff --git a/src/soc/intel/jasperlake/include/soc/itss.h b/src/soc/intel/jasperlake/include/soc/itss.h
index 39794ead73..97430022f3 100644
--- a/src/soc/intel/jasperlake/include/soc/itss.h
+++ b/src/soc/intel/jasperlake/include/soc/itss.h
@@ -12,8 +12,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef SOC_INTEL_TGL_ITSS_H
-#define SOC_INTEL_TGL_ITSS_H
+#ifndef SOC_INTEL_JSL_ITSS_H
+#define SOC_INTEL_JSL_ITSS_H
 
 #define GPIO_IRQ_START	50
 #define GPIO_IRQ_END	ITSS_MAX_IRQ
@@ -22,4 +22,4 @@
 #define IRQS_PER_IPC	32
 #define NUM_IPC_REGS	((ITSS_MAX_IRQ + IRQS_PER_IPC - 1)/IRQS_PER_IPC)
 
-#endif	/* SOC_INTEL_TGL_ITSS_H */
+#endif	/* SOC_INTEL_JSL_ITSS_H */
diff --git a/src/soc/intel/jasperlake/include/soc/me.h b/src/soc/intel/jasperlake/include/soc/me.h
index 94331b4c9e..0fab6d582a 100644
--- a/src/soc/intel/jasperlake/include/soc/me.h
+++ b/src/soc/intel/jasperlake/include/soc/me.h
@@ -12,8 +12,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef _TIGERLAKE_ME_H_
-#define _TIGERLAKE_ME_H_
+#ifndef _JASPERLAKE_ME_H_
+#define _JASPERLAKE_ME_H_
 
 /* ME Host Firmware Status register 1 */
 union me_hfsts1 {
@@ -52,4 +52,4 @@ union me_hfsts3 {
 		u32 reserved_30: 2;
 	} __packed fields;
 };
-#endif /* _TIGERLAKE_ME_H_ */
+#endif /* _JASPERLAKE_ME_H_ */
diff --git a/src/soc/intel/jasperlake/include/soc/meminit_jsl.h b/src/soc/intel/jasperlake/include/soc/meminit.h
index 421e31d8e4..0e2a46c0e5 100644
--- a/src/soc/intel/jasperlake/include/soc/meminit_jsl.h
+++ b/src/soc/intel/jasperlake/include/soc/meminit.h
@@ -12,8 +12,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef _SOC_JASPERLAKE_MEMCFG_INIT_H_
-#define _SOC_JASPERLAKE_MEMCFG_INIT_H_
+#ifndef _SOC_JASPERLAKE_MEMINIT_H_
+#define _SOC_JASPERLAKE_MEMINIT_H_
 
 #include <types.h>
 #include <fsp/soc_binding.h>
@@ -121,4 +121,4 @@ struct mb_cfg {
 void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *board_cfg,
 			const struct spd_info *spd_info, bool half_populated);
 
-#endif /* _SOC_JASPERLAKE_MEMCFG_INIT_H_ */
+#endif /* _SOC_JASPERLAKE_MEMINIT_H_ */
diff --git a/src/soc/intel/jasperlake/include/soc/meminit_tgl.h b/src/soc/intel/jasperlake/include/soc/meminit_tgl.h
deleted file mode 100644
index 5573fb7110..0000000000
--- a/src/soc/intel/jasperlake/include/soc/meminit_tgl.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- *
- * SPDX-License-Identifier: GPL-2.0-or-later
- */
-
-#ifndef _SOC_MEMINIT_TGL_H_
-#define _SOC_MEMINIT_TGL_H_
-
-#include <stddef.h>
-#include <stdint.h>
-#include <fsp/soc_binding.h>
-
-#define BYTES_PER_CHANNEL	2
-#define BITS_PER_BYTE		8
-#define DQS_PER_CHANNEL		2
-#define NUM_CHANNELS		8
-
-struct spd_by_pointer {
-	size_t spd_data_len;
-	uintptr_t spd_data_ptr;
-};
-
-enum mem_info_read_type {
-	NOT_EXISTING,	/* No memory in this channel */
-	READ_SPD_CBFS,	/* Find spd file in CBFS. */
-	READ_SPD_MEMPTR	/* Find spd data from pointer. */
-};
-
-struct spd_info {
-	enum mem_info_read_type read_type;
-	union spd_data_by {
-		/* To identify spd file when read_type is READ_SPD_CBFS. */
-		int spd_index;
-
-		/* To find spd data when read_type is READ_SPD_MEMPTR. */
-		struct spd_by_pointer spd_data_ptr_info;
-	} spd_spec;
-};
-
-/* Board-specific memory configuration information */
-struct mb_lpddr4x_cfg {
-	/* DQ mapping */
-	uint8_t dq_map[NUM_CHANNELS][BYTES_PER_CHANNEL * BITS_PER_BYTE];
-
-	/*
-	 * DQS CPU<>DRAM map.  Each array entry represents a
-	 * mapping of a dq bit on the CPU to the bit it's connected to on
-	 * the memory part.  The array index represents the dqs bit number
-	 * on the memory part, and the values in the array represent which
-	 * pin on the CPU that DRAM pin connects to.
-	 */
-	uint8_t dqs_map[NUM_CHANNELS][DQS_PER_CHANNEL];
-
-	/*
-	 * Early Command Training Enable/Disable Control
-	 * 1 = enable, 0 = disable
-	 */
-	uint8_t ect;
-};
-
-/* Initialize default memory configurations for dimm0-only lpddr4x */
-void meminit_lpddr4x_dimm0(FSP_M_CONFIG *mem_cfg,
-			   const struct mb_lpddr4x_cfg *board_cfg,
-			   const struct spd_info *spd,
-			   bool half_populated);
-
-#endif /* _SOC_MEMINIT_TGL_H_ */
diff --git a/src/soc/intel/jasperlake/include/soc/p2sb.h b/src/soc/intel/jasperlake/include/soc/p2sb.h
index d483ee399b..2fca70556c 100644
--- a/src/soc/intel/jasperlake/include/soc/p2sb.h
+++ b/src/soc/intel/jasperlake/include/soc/p2sb.h
@@ -12,14 +12,8 @@
  * GNU General Public License for more details.
  */
 
-/*
- * This file is created based on Intel Tiger Lake Processor PCH Datasheet
- * Document number: 575857
- * Chapter number: 3
- */
-
-#ifndef _SOC_TIGERLAKE_P2SB_H_
-#define _SOC_TIGERLAKE_P2SB_H_
+#ifndef _SOC_JASPERLAKE_P2SB_H_
+#define _SOC_JASPERLAKE_P2SB_H_
 
 #define HPTC_OFFSET			0x60
 #define HPTC_ADDR_ENABLE_BIT		(1 << 7)
diff --git a/src/soc/intel/jasperlake/include/soc/pch.h b/src/soc/intel/jasperlake/include/soc/pch.h
index c2f497c1c8..ccfc44942b 100644
--- a/src/soc/intel/jasperlake/include/soc/pch.h
+++ b/src/soc/intel/jasperlake/include/soc/pch.h
@@ -12,15 +12,11 @@
  * GNU General Public License for more details.
  */
 
-#ifndef _SOC_TIGERLAKE_PCH_H_
-#define _SOC_TIGERLAKE_PCH_H_
+#ifndef _SOC_JASPERLAKE_PCH_H_
+#define _SOC_JASPERLAKE_PCH_H_
 
 #include <stdint.h>
 
-#define PCH_TGP				1
-#define PCH_JSP				2
-#define PCH_UNKNOWN_SERIES		0xFF
-
 #define PCIE_CLK_NOTUSED		0xFF
 #define PCIE_CLK_LAN			0x70
 #define PCIE_CLK_FREE			0x80
diff --git a/src/soc/intel/jasperlake/include/soc/pci_devs.h b/src/soc/intel/jasperlake/include/soc/pci_devs.h
index e729864817..139d1827f5 100644
--- a/src/soc/intel/jasperlake/include/soc/pci_devs.h
+++ b/src/soc/intel/jasperlake/include/soc/pci_devs.h
@@ -12,8 +12,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef _SOC_TIGERLAKE_PCI_DEVS_H_
-#define _SOC_TIGERLAKE_PCI_DEVS_H_
+#ifndef _SOC_JASPERLAKE_PCI_DEVS_H_
+#define _SOC_JASPERLAKE_PCI_DEVS_H_
 
 #include <device/pci_def.h>
 
@@ -88,11 +88,8 @@
 #define  PCH_DEV_USBOTG		_PCH_DEV(XHCI, 1)
 #define  PCH_DEV_SRAM		_PCH_DEV(XHCI, 2)
 #define  PCH_DEV_CNVI_WIFI	_PCH_DEV(XHCI, 3)
-
-#if CONFIG(SOC_INTEL_JASPERLAKE_COPY)
 #define  PCH_DEVFN_SDCARD	_PCH_DEVFN(XHCI, 5)
 #define  PCH_DEV_SDCARD		_PCH_DEV(XHCI, 5)
-#endif
 
 #define PCH_DEV_SLOT_SIO3	0x15
 #define  PCH_DEVFN_I2C0		_PCH_DEVFN(SIO3, 0)
@@ -130,11 +127,9 @@
 #define  PCH_DEV_I2C5		_PCH_DEV(SIO4, 1)
 #define  PCH_DEV_UART2		_PCH_DEV(SIO4, 2)
 
-#if CONFIG(SOC_INTEL_JASPERLAKE_COPY)
 #define PCH_DEV_SLOT_STORAGE	0x1a
 #define  PCH_DEVFN_EMMC		_PCH_DEVFN(STORAGE, 0)
 #define  PCH_DEV_EMMC		_PCH_DEV(STORAGE, 0)
-#endif
 
 #define PCH_DEV_SLOT_PCIE	0x1c
 #define  PCH_DEVFN_PCIE1	_PCH_DEVFN(PCIE, 0)
diff --git a/src/soc/intel/jasperlake/include/soc/pcr_ids.h b/src/soc/intel/jasperlake/include/soc/pcr_ids.h
index 4143892f87..32ff6ba78a 100644
--- a/src/soc/intel/jasperlake/include/soc/pcr_ids.h
+++ b/src/soc/intel/jasperlake/include/soc/pcr_ids.h
@@ -12,14 +12,8 @@
  * GNU General Public License for more details.
  */
 
-/*
- * This file is created based on Intel Tiger Lake Processor PCH Datasheet
- * Document number: 575857
- * Chapter number: 31-35
- */
-
-#ifndef SOC_TIGERLAKE_PCR_H
-#define SOC_TIGERLAKE_PCR_H
+#ifndef SOC_JASPERLAKE_PCR_H
+#define SOC_JASPERLAKE_PCR_H
 /*
  * Port ids
  */
diff --git a/src/soc/intel/jasperlake/include/soc/pm.h b/src/soc/intel/jasperlake/include/soc/pm.h
index 14fa5d0c08..5fb15940ca 100644
--- a/src/soc/intel/jasperlake/include/soc/pm.h
+++ b/src/soc/intel/jasperlake/include/soc/pm.h
@@ -12,12 +12,6 @@
  * GNU General Public License for more details.
  */
 
-/*
- * This file is created based on Intel Tiger Lake Processor PCH Datasheet
- * Document number: 575857
- * Chapter number: 4
- */
-
 #ifndef _SOC_PM_H_
 #define _SOC_PM_H_
 
diff --git a/src/soc/intel/jasperlake/include/soc/pmc.h b/src/soc/intel/jasperlake/include/soc/pmc.h
index 0ec1d36e44..43c87de45f 100644
--- a/src/soc/intel/jasperlake/include/soc/pmc.h
+++ b/src/soc/intel/jasperlake/include/soc/pmc.h
@@ -12,8 +12,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef _SOC_TIGERLAKE_PMC_H_
-#define _SOC_TIGERLAKE_PMC_H_
+#ifndef _SOC_JASPERLAKE_PMC_H_
+#define _SOC_JASPERLAKE_PMC_H_
 
 /* PCI Configuration Space (D31:F2): PMC */
 #define  PWRMBASE		0x10
@@ -114,35 +114,16 @@
 #define  GPE0_DWX_MASK			0xf
 #define  GPE0_DW_SHIFT(x)		(4*(x))
 
-#if CONFIG(SOC_INTEL_TIGERLAKE_COPY)
-
-	#define  PMC_GPP_B			0x0
-	#define  PMC_GPP_T			0x1
-	#define  PMC_GPP_A			0x2
-	#define  PMC_GPP_R			0x3
-	#define  PMC_GPD			0x4
-	#define  PMC_GPP_S			0x5
-	#define  PMC_GPP_H			0x6
-	#define  PMC_GPP_D			0x7
-	#define  PMC_GPP_U			0x8
-	#define  PMC_GPP_F			0xA
-	#define  PMC_GPP_C			0xB
-	#define  PMC_GPP_E			0xC
-
-#elif CONFIG(SOC_INTEL_JASPERLAKE_COPY)
-
-	#define  PMC_GPP_A			0x0
-	#define  PMC_GPP_B			0x1
-	#define  PMC_GPP_F			0x2
-	#define  PMC_GPD			0x3
-	#define  PMC_GPP_R			0x4
-	#define  PMC_GPP_S			0x6
-	#define  PMC_GPP_D			0x7
-	#define  PMC_GPP_C			0x8
-	#define  PMC_GPP_H			0xA
-	#define  PMC_GPP_E			0xF
-
-#endif
+#define  PMC_GPP_A			0x0
+#define  PMC_GPP_B			0x1
+#define  PMC_GPP_F			0x2
+#define  PMC_GPD			0x3
+#define  PMC_GPP_R			0x4
+#define  PMC_GPP_S			0x6
+#define  PMC_GPP_D			0x7
+#define  PMC_GPP_C			0x8
+#define  PMC_GPP_H			0xA
+#define  PMC_GPP_E			0xF
 
 #define GBLRST_CAUSE0			0x1924
 #define   GBLRST_CAUSE0_THERMTRIP	(1 << 5)
diff --git a/src/soc/intel/jasperlake/include/soc/smbus.h b/src/soc/intel/jasperlake/include/soc/smbus.h
index 3fb8291698..fb19772e73 100644
--- a/src/soc/intel/jasperlake/include/soc/smbus.h
+++ b/src/soc/intel/jasperlake/include/soc/smbus.h
@@ -12,14 +12,8 @@
  * GNU General Public License for more details.
  */
 
-/*
- * This file is created based on Intel Tiger Lake Processor PCH Datasheet
- * Document number: 575857
- * Chapter number: 6
- */
-
-#ifndef _SOC_TIGERLAKE_SMBUS_H_
-#define _SOC_TIGERLAKE_SMBUS_H_
+#ifndef _SOC_JASPERLAKE_SMBUS_H_
+#define _SOC_JASPERLAKE_SMBUS_H_
 
 /* IO and MMIO registers under primary BAR */
 
diff --git a/src/soc/intel/jasperlake/include/soc/soc_chip.h b/src/soc/intel/jasperlake/include/soc/soc_chip.h
index 250aa9a0aa..d4e9be6d04 100644
--- a/src/soc/intel/jasperlake/include/soc/soc_chip.h
+++ b/src/soc/intel/jasperlake/include/soc/soc_chip.h
@@ -12,9 +12,9 @@
  * GNU General Public License for more details.
  */
 
-#ifndef _SOC_TIGERLAKE_SOC_CHIP_H_
-#define _SOC_TIGERLAKE_SOC_CHIP_H_
+#ifndef _SOC_JASPERLAKE_SOC_CHIP_H_
+#define _SOC_JASPERLAKE_SOC_CHIP_H_
 
 #include "../../chip.h"
 
-#endif /* _SOC_TIGERLAKE_SOC_CHIP_H_ */
+#endif /* _SOC_JASPERLAKE_SOC_CHIP_H_ */
diff --git a/src/soc/intel/jasperlake/include/soc/systemagent.h b/src/soc/intel/jasperlake/include/soc/systemagent.h
index d8c8ad47da..67ce880988 100644
--- a/src/soc/intel/jasperlake/include/soc/systemagent.h
+++ b/src/soc/intel/jasperlake/include/soc/systemagent.h
@@ -12,14 +12,8 @@
  * GNU General Public License for more details.
  */
 
-/*
- * This file is created based on Intel Tiger Lake Processor SA Datasheet
- * Document number: 571131
- * Chapter number: 3
- */
-
-#ifndef SOC_TIGERLAKE_SYSTEMAGENT_H
-#define SOC_TIGERLAKE_SYSTEMAGENT_H
+#ifndef SOC_JASPERLAKE_SYSTEMAGENT_H
+#define SOC_JASPERLAKE_SYSTEMAGENT_H
 
 #include <intelblocks/systemagent.h>
 
diff --git a/src/soc/intel/jasperlake/lockdown.c b/src/soc/intel/jasperlake/lockdown.c
index 18d4fa728e..7ad5e4aa69 100644
--- a/src/soc/intel/jasperlake/lockdown.c
+++ b/src/soc/intel/jasperlake/lockdown.c
@@ -12,12 +12,6 @@
  * GNU General Public License for more details.
  */
 
-/*
- * This file is created based on Intel Tiger Lake Processor PCH Datasheet
- * Document number: 575857
- * Chapter number: 4
- */
-
 #include <device/mmio.h>
 #include <intelblocks/cfg.h>
 #include <intelpch/lockdown.h>
diff --git a/src/soc/intel/jasperlake/meminit_jsl.c b/src/soc/intel/jasperlake/meminit.c
index c68d2100fc..88b39240bf 100644
--- a/src/soc/intel/jasperlake/meminit_jsl.c
+++ b/src/soc/intel/jasperlake/meminit.c
@@ -15,7 +15,7 @@
 #include <assert.h>
 #include <console/console.h>
 #include <fsp/util.h>
-#include <soc/meminit_jsl.h>
+#include <soc/meminit.h>
 #include <spd_bin.h>
 #include <string.h>
 
diff --git a/src/soc/intel/jasperlake/meminit_tgl.c b/src/soc/intel/jasperlake/meminit_tgl.c
deleted file mode 100644
index a0e5107998..0000000000
--- a/src/soc/intel/jasperlake/meminit_tgl.c
+++ /dev/null
@@ -1,163 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- *
- * SPDX-License-Identifier: GPL-2.0-or-later
- */
-
-#include <assert.h>
-#include <console/console.h>
-#include <fsp/util.h>
-#include <soc/meminit_tgl.h>
-#include <spd_bin.h>
-#include <string.h>
-
-enum dimm_enable_options {
-	ENABLE_BOTH_DIMMS = 0,
-	DISABLE_DIMM0 = 1,
-	DISABLE_DIMM1 = 2,
-	DISABLE_BOTH_DIMMS = 3
-};
-
-#define MEM_INIT_CH_DQ_DQS_MAP(_mem_cfg, _b_cfg, _ch)		\
-	do {							\
-		memcpy(&_mem_cfg->DqMapCpu2DramCh ## _ch,	\
-		       &_b_cfg->dq_map[_ch],			\
-			sizeof(_b_cfg->dq_map[_ch]));		\
-		memcpy(&_mem_cfg->DqsMapCpu2DramCh ## _ch,	\
-			&_b_cfg->dqs_map[_ch],			\
-			sizeof(_b_cfg->dqs_map[_ch]));		\
-	} while (0)
-
-
-static void spd_read_from_cbfs(const struct spd_info *spd,
-			       uintptr_t *spd_data_ptr, size_t *spd_data_len)
-{
-	struct region_device spd_rdev;
-	size_t spd_index = spd->spd_spec.spd_index;
-
-	printk(BIOS_DEBUG, "SPD INDEX = %lu\n", spd_index);
-	if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0)
-		die("spd.bin not found or incorrect index\n");
-
-	*spd_data_len = region_device_sz(&spd_rdev);
-
-	/* Memory leak is ok since we have memory mapped boot media */
-	assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED));
-
-	*spd_data_ptr = (uintptr_t)rdev_mmap_full(&spd_rdev);
-}
-
-static void get_spd_data(const struct spd_info *spd,
-			 uintptr_t *spd_data_ptr, size_t *spd_data_len)
-{
-	if (spd->read_type == READ_SPD_MEMPTR) {
-		*spd_data_ptr = spd->spd_spec.spd_data_ptr_info.spd_data_ptr;
-		*spd_data_len = spd->spd_spec.spd_data_ptr_info.spd_data_len;
-		return;
-	}
-
-	if (spd->read_type == READ_SPD_CBFS) {
-		spd_read_from_cbfs(spd, spd_data_ptr, spd_data_len);
-		return;
-	}
-
-	die("no valid way to read SPD info");
-}
-
-static void meminit_dq_dqs_map(FSP_M_CONFIG *mem_cfg,
-			       const struct mb_lpddr4x_cfg *board_cfg,
-			       bool half_populated)
-{
-	MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 0);
-	MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 1);
-	MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 2);
-	MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 3);
-
-	if (half_populated)
-		return;
-
-	MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 4);
-	MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 5);
-	MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 6);
-	MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 7);
-}
-
-static void meminit_channels_dimm0(FSP_M_CONFIG *mem_cfg,
-				   const struct mb_lpddr4x_cfg *board_cfg,
-				   uintptr_t spd_data_ptr,
-				   bool half_populated)
-{
-	uint8_t dimm_cfg = DISABLE_DIMM1; /* Use only DIMM0 */
-
-	/* Channel 0 */
-	mem_cfg->Reserved9[0] = dimm_cfg;
-	mem_cfg->MemorySpdPtr00 = spd_data_ptr;
-	mem_cfg->MemorySpdPtr01 = 0;
-
-	/* Channel 1 */
-	mem_cfg->Reserved9[1] = dimm_cfg;
-	mem_cfg->MemorySpdPtr02 = spd_data_ptr;
-	mem_cfg->MemorySpdPtr03 = 0;
-
-	/* Channel 2 */
-	mem_cfg->Reserved9[2] = dimm_cfg;
-	mem_cfg->MemorySpdPtr04 = spd_data_ptr;
-	mem_cfg->MemorySpdPtr05 = 0;
-
-	/* Channel 3 */
-	mem_cfg->Reserved9[3] = dimm_cfg;
-	mem_cfg->MemorySpdPtr06 = spd_data_ptr;
-	mem_cfg->MemorySpdPtr07 = 0;
-
-	if (half_populated) {
-		printk(BIOS_INFO, "%s: DRAM half-populated\n", __func__);
-		dimm_cfg = DISABLE_BOTH_DIMMS;
-		spd_data_ptr = 0;
-	}
-
-	/* Channel 4 */
-	mem_cfg->Reserved9[4] = dimm_cfg;
-	mem_cfg->MemorySpdPtr08 = spd_data_ptr;
-	mem_cfg->MemorySpdPtr09 = 0;
-
-	/* Channel 5 */
-	mem_cfg->Reserved9[5] = dimm_cfg;
-	mem_cfg->MemorySpdPtr10 = spd_data_ptr;
-	mem_cfg->MemorySpdPtr11 = 0;
-
-	/* Channel 6 */
-	mem_cfg->Reserved9[6] = dimm_cfg;
-	mem_cfg->MemorySpdPtr12 = spd_data_ptr;
-	mem_cfg->MemorySpdPtr13 = 0;
-
-	/* Channel 7 */
-	mem_cfg->Reserved9[7] = dimm_cfg;
-	mem_cfg->MemorySpdPtr14 = spd_data_ptr;
-	mem_cfg->MemorySpdPtr15 = 0;
-
-	meminit_dq_dqs_map(mem_cfg, board_cfg, half_populated);
-}
-
-/* Initialize onboard memory configurations for lpddr4x */
-void meminit_lpddr4x_dimm0(FSP_M_CONFIG *mem_cfg,
-			   const struct mb_lpddr4x_cfg *board_cfg,
-			   const struct spd_info *spd,
-			   bool half_populated)
-
-{
-	size_t spd_data_len;
-	uintptr_t spd_data_ptr;
-
-	get_spd_data(spd, &spd_data_ptr, &spd_data_len);
-	print_spd_info((unsigned char *)spd_data_ptr);
-
-	mem_cfg->MemorySpdDataLen = spd_data_len;
-	meminit_channels_dimm0(mem_cfg, board_cfg, spd_data_ptr,
-			       half_populated);
-
-	/* LPDDR4 does not allow interleaved memory */
-	mem_cfg->DqPinsInterleaved = 0;
-	mem_cfg->ECT = board_cfg->ect;
-	mem_cfg->MrcSafeConfig = 0x1;
-}
diff --git a/src/soc/intel/jasperlake/p2sb.c b/src/soc/intel/jasperlake/p2sb.c
index 64f181f634..328c4d3bab 100644
--- a/src/soc/intel/jasperlake/p2sb.c
+++ b/src/soc/intel/jasperlake/p2sb.c
@@ -12,12 +12,6 @@
  * GNU General Public License for more details.
  */
 
-/*
- * This file is created based on Intel Tiger Lake Processor PCH Datasheet
- * Document number: 575857
- * Chapter number: 3
- */
-
 #include <console/console.h>
 #include <intelblocks/p2sb.h>
 
diff --git a/src/soc/intel/jasperlake/pmc.c b/src/soc/intel/jasperlake/pmc.c
index 13902b80a6..4667f1d905 100644
--- a/src/soc/intel/jasperlake/pmc.c
+++ b/src/soc/intel/jasperlake/pmc.c
@@ -12,12 +12,6 @@
  * GNU General Public License for more details.
  */
 
-/*
- * This file is created based on Intel Tiger Lake Processor PCH Datasheet
- * Document number: 575857
- * Chapter number: 4
- */
-
 #include <bootstate.h>
 #include <console/console.h>
 #include <device/mmio.h>
diff --git a/src/soc/intel/jasperlake/pmutil.c b/src/soc/intel/jasperlake/pmutil.c
index ac254020cb..4134a2b7fc 100644
--- a/src/soc/intel/jasperlake/pmutil.c
+++ b/src/soc/intel/jasperlake/pmutil.c
@@ -17,13 +17,6 @@
  * and the differences between PCH variants.
  */
 
-/*
- * This file is created based on Intel Tiger Lake Processor PCH Datasheet
- * Document number: 575857
- * Chapter number: 4
- */
-
-
 #define __SIMPLE_DEVICE__
 
 #include <device/mmio.h>
@@ -183,7 +176,7 @@ uint32_t *soc_pmc_etr_addr(void)
 
 void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2)
 {
-	DEVTREE_CONST struct soc_intel_tigerlake_config *config;
+	DEVTREE_CONST struct soc_intel_jasperlake_config *config;
 
 	config = config_of_soc();
 
diff --git a/src/soc/intel/jasperlake/romstage/Makefile.inc b/src/soc/intel/jasperlake/romstage/Makefile.inc
index ff32916433..5a8322b055 100644
--- a/src/soc/intel/jasperlake/romstage/Makefile.inc
+++ b/src/soc/intel/jasperlake/romstage/Makefile.inc
@@ -12,8 +12,7 @@
 # GNU General Public License for more details.
 #
 
-romstage-$(CONFIG_SOC_INTEL_TIGERLAKE_COPY) += fsp_params_tgl.c
-romstage-$(CONFIG_SOC_INTEL_JASPERLAKE_COPY) += fsp_params_jsl.c
+romstage-y += fsp_params.c
 romstage-y += ../../../../cpu/intel/car/romstage.c
 romstage-y += romstage.c
 romstage-y += pch.c
diff --git a/src/soc/intel/jasperlake/romstage/fsp_params_jsl.c b/src/soc/intel/jasperlake/romstage/fsp_params.c
index 18253aac9c..ca7ff26a0e 100644
--- a/src/soc/intel/jasperlake/romstage/fsp_params_jsl.c
+++ b/src/soc/intel/jasperlake/romstage/fsp_params.c
@@ -21,7 +21,7 @@
 #include <string.h>
 
 static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
-		const struct soc_intel_tigerlake_config *config)
+		const struct soc_intel_jasperlake_config *config)
 {
 	unsigned int i;
 	const struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD);
@@ -89,7 +89,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
 	m_cfg->SmbusEnable = config->SmbusEnable;
 
 	/* Set debug probe type */
-	m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_TIGERLAKE_COPY_DEBUG_CONSENT;
+	m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_JASPERLAKE_COPY_DEBUG_CONSENT;
 
 	/* VT-d config */
 	m_cfg->VtdDisable = 0;
@@ -131,7 +131,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
 
 void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 {
-	const struct soc_intel_tigerlake_config *config = config_of_soc();
+	const struct soc_intel_jasperlake_config *config = config_of_soc();
 	FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
 
 	soc_memory_init_params(m_cfg, config);
diff --git a/src/soc/intel/jasperlake/romstage/fsp_params_tgl.c b/src/soc/intel/jasperlake/romstage/fsp_params_tgl.c
deleted file mode 100644
index ac1a507270..0000000000
--- a/src/soc/intel/jasperlake/romstage/fsp_params_tgl.c
+++ /dev/null
@@ -1,208 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <assert.h>
-#include <console/console.h>
-#include <cpu/x86/msr.h>
-#include <fsp/util.h>
-#include <soc/gpio_soc_defs.h>
-#include <soc/iomap.h>
-#include <soc/msr.h>
-#include <soc/pci_devs.h>
-#include <soc/romstage.h>
-#include <soc/soc_chip.h>
-#include <string.h>
-
-static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
-		const struct soc_intel_tigerlake_config *config)
-{
-	unsigned int i;
-	uint32_t mask = 0;
-	const struct device *dev;
-
-	/* Set IGD stolen size to 60MB. */
-	m_cfg->IgdDvmt50PreAlloc = 0xFE;
-	m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;
-	m_cfg->IedSize = CONFIG_IED_REGION_SIZE;
-	m_cfg->SaGv = config->SaGv;
-	m_cfg->UserBd = BOARD_TYPE_ULT_ULX;
-	m_cfg->RMT = config->RMT;
-
-	/* CpuRatio Settings */
-	if (config->cpu_ratio_override) {
-		m_cfg->CpuRatio = config->cpu_ratio_override;
-	} else {
-		/* Set CpuRatio to match existing MSR value */
-		msr_t flex_ratio;
-		flex_ratio = rdmsr(MSR_FLEX_RATIO);
-		m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff;
-	}
-
-	for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {
-		if (config->PcieRpEnable[i])
-			mask |= (1 << i);
-	}
-	m_cfg->PcieRpEnableMask = mask;
-
-	memcpy(m_cfg->PcieClkSrcUsage, config->PcieClkSrcUsage,
-		sizeof(config->PcieClkSrcUsage));
-
-	for (i = 0; i < CONFIG_MAX_PCIE_CLOCKS; i++) {
-		if (config->PcieClkSrcUsage[i] == 0)
-			m_cfg->PcieClkSrcUsage[i] = 0xff;
-	}
-
-	memcpy(m_cfg->PcieClkSrcClkReq, config->PcieClkSrcClkReq,
-		sizeof(config->PcieClkSrcClkReq));
-
-	m_cfg->PrmrrSize = config->PrmrrSize;
-	m_cfg->EnableC6Dram = config->enable_c6dram;
-	/* Disable BIOS Guard */
-	m_cfg->BiosGuard = 0;
-
-	/* UART Debug Log */
-	m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ?
-			DEBUG_INTERFACE_UART|DEBUG_INTERFACE_TRACEHUB :
-			DEBUG_INTERFACE_SERIAL_IO|DEBUG_INTERFACE_TRACEHUB;
-	m_cfg->PcdIsaSerialUartBase = 0x0;
-	m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE;
-
-	/*
-	 * Skip IGD initialization in FSP if device
-	 * is disable in devicetree.cb.
-	 */
-	dev = pcidev_path_on_root(SA_DEVFN_IGD);
-	if (!dev || !dev->enabled)
-		m_cfg->InternalGfx = 0;
-	else
-		m_cfg->InternalGfx = 0x1;
-
-	/* ISH */
-	dev = pcidev_path_on_root(PCH_DEVFN_ISH);
-	if (!dev || !dev->enabled)
-		m_cfg->PchIshEnable = 0;
-	else
-		m_cfg->PchIshEnable = 1;
-
-	/* DP port config */
-	m_cfg->DdiPortAConfig = config->DdiPortAConfig;
-	m_cfg->DdiPortBConfig = config->DdiPortBConfig;
-	m_cfg->DdiPortAHpd = config->DdiPortAHpd;
-	m_cfg->DdiPortBHpd = config->DdiPortBHpd;
-	m_cfg->DdiPortCHpd = config->DdiPortCHpd;
-	m_cfg->DdiPort1Hpd = config->DdiPort1Hpd;
-	m_cfg->DdiPort2Hpd = config->DdiPort2Hpd;
-	m_cfg->DdiPort3Hpd = config->DdiPort3Hpd;
-	m_cfg->DdiPort4Hpd = config->DdiPort4Hpd;
-	m_cfg->DdiPortADdc = config->DdiPortADdc;
-	m_cfg->DdiPortBDdc = config->DdiPortBDdc;
-	m_cfg->DdiPortCDdc = config->DdiPortCDdc;
-	m_cfg->DdiPort1Ddc = config->DdiPort1Ddc;
-	m_cfg->DdiPort2Ddc = config->DdiPort2Ddc;
-	m_cfg->DdiPort3Ddc = config->DdiPort3Ddc;
-	m_cfg->DdiPort4Ddc = config->DdiPort4Ddc;
-
-	/* Image clock: disable all clocks for bypassing FSP pin mux */
-	memset(m_cfg->ImguClkOutEn, 0, sizeof(m_cfg->ImguClkOutEn));
-
-	/* Tcss */
-	m_cfg->TcssXhciEn = config->TcssXhciEn;
-	m_cfg->TcssXdciEn = config->TcssXdciEn;
-
-	/* USB4/TBT */
-	dev = pcidev_path_on_root(SA_DEVFN_TBT0);
-	if (dev)
-		m_cfg->TcssItbtPcie0En = dev->enabled;
-	else
-		m_cfg->TcssItbtPcie0En = 0;
-	dev = pcidev_path_on_root(SA_DEVFN_TBT1);
-	if (dev)
-		m_cfg->TcssItbtPcie1En = dev->enabled;
-	else
-		m_cfg->TcssItbtPcie1En = 0;
-
-	dev = pcidev_path_on_root(SA_DEVFN_TBT2);
-	if (dev)
-		m_cfg->TcssItbtPcie2En = dev->enabled;
-	else
-		m_cfg->TcssItbtPcie2En = 0;
-	dev = pcidev_path_on_root(SA_DEVFN_TBT3);
-	if (dev)
-		m_cfg->TcssItbtPcie3En = dev->enabled;
-	else
-		m_cfg->TcssItbtPcie3En = 0;
-
-	/* Enable Hyper Threading */
-	m_cfg->HyperThreading = 1;
-	/* Disable Lock PCU Thermal Management registers */
-	m_cfg->LockPTMregs = 0;
-	/* Channel Hash Mask:0x0001=BIT6 set(Minimal), 0x3FFF=BIT[19:6] set(Maximum) */
-	m_cfg->ChHashMask = 0x30CC;
-	/* Enable SMBus controller based on config */
-	m_cfg->SmbusEnable = config->SmbusEnable;
-	/* Set debug probe type */
-	m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_TIGERLAKE_COPY_DEBUG_CONSENT;
-
-	/* Audio: HDAUDIO_LINK_MODE I2S/SNDW */
-	dev = pcidev_path_on_root(PCH_DEVFN_HDA);
-	if (!dev)
-		m_cfg->PchHdaEnable = 0;
-	else
-		m_cfg->PchHdaEnable = dev->enabled;
-
-	m_cfg->PchHdaDspEnable = config->PchHdaDspEnable;
-	m_cfg->PchHdaAudioLinkHdaEnable = config->PchHdaAudioLinkHdaEnable;
-	memcpy(m_cfg->PchHdaAudioLinkDmicEnable, config->PchHdaAudioLinkDmicEnable,
-			sizeof(m_cfg->PchHdaAudioLinkDmicEnable));
-	memcpy(m_cfg->PchHdaAudioLinkSspEnable, config->PchHdaAudioLinkSspEnable,
-			sizeof(m_cfg->PchHdaAudioLinkSspEnable));
-	memcpy(m_cfg->PchHdaAudioLinkSndwEnable, config->PchHdaAudioLinkSndwEnable,
-			sizeof(m_cfg->PchHdaAudioLinkSndwEnable));
-	m_cfg->PchHdaIDispLinkTmode = config->PchHdaIDispLinkTmode;
-	m_cfg->PchHdaIDispLinkFrequency = config->PchHdaIDispLinkFrequency;
-	m_cfg->PchHdaIDispCodecDisconnect = config->PchHdaIDispCodecDisconnect;
-
-	/* Vt-D config */
-	m_cfg->VtdDisable = 0;
-	m_cfg->VtdIgdEnable = 0x1;
-	m_cfg->VtdBaseAddress[0] = GFXVT_BASE_ADDRESS;
-	m_cfg->VtdIpuEnable = 0x1;
-	m_cfg->VtdBaseAddress[1] = IPUVT_BASE_ADDRESS;
-	m_cfg->VtdIopEnable = 0x1;
-	m_cfg->VtdBaseAddress[2] = VTVC0_BASE_ADDRESS;
-	m_cfg->VtdItbtEnable = 0x1;
-	m_cfg->VtdBaseAddress[3] = TBT0_BASE_ADDRESS;
-	m_cfg->VtdBaseAddress[4] = TBT1_BASE_ADDRESS;
-	m_cfg->VtdBaseAddress[5] = TBT2_BASE_ADDRESS;
-	m_cfg->VtdBaseAddress[6] = TBT3_BASE_ADDRESS;
-
-	/* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */
-	m_cfg->VmxEnable = CONFIG(ENABLE_VMX);
-}
-
-void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
-{
-	const struct soc_intel_tigerlake_config *config;
-	FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
-
-	config = config_of_soc();
-
-	soc_memory_init_params(m_cfg, config);
-	mainboard_memory_init_params(mupd);
-}
-
-__weak void mainboard_memory_init_params(FSPM_UPD *mupd)
-{
-	printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
-}
diff --git a/src/soc/intel/jasperlake/romstage/systemagent.c b/src/soc/intel/jasperlake/romstage/systemagent.c
index 9fa498e802..3cf61bd731 100644
--- a/src/soc/intel/jasperlake/romstage/systemagent.c
+++ b/src/soc/intel/jasperlake/romstage/systemagent.c
@@ -12,12 +12,6 @@
  * GNU General Public License for more details.
  */
 
-/*
- * This file is created based on Intel Tiger Lake Processor SA Datasheet
- * Document number: 571131
- * Chapter number: 3
- */
-
 #include <intelblocks/systemagent.h>
 #include <soc/iomap.h>
 #include <soc/romstage.h>
diff --git a/src/soc/intel/jasperlake/sd.c b/src/soc/intel/jasperlake/sd.c
index 9898734f3d..d97b63f498 100644
--- a/src/soc/intel/jasperlake/sd.c
+++ b/src/soc/intel/jasperlake/sd.c
@@ -12,12 +12,6 @@
  * GNU General Public License for more details.
  */
 
-/*
- * This file is created based on Intel Tiger Lake Processor PCH Datasheet
- * Document number: 575857
- * Chapter number: 26
- */
-
 #include <intelblocks/sd.h>
 #include <soc/soc_chip.h>
 
diff --git a/src/soc/intel/jasperlake/smihandler.c b/src/soc/intel/jasperlake/smihandler.c
index 67e59a26a0..3f6cfd2d7f 100644
--- a/src/soc/intel/jasperlake/smihandler.c
+++ b/src/soc/intel/jasperlake/smihandler.c
@@ -24,12 +24,12 @@
  * Specific SOC SMI handler during ramstage finalize phase
  *
  * BIOS can't make CSME function disable as is due to POSTBOOT_SAI
- * restriction in place from TGP chipset. Hence create SMI Handler to
+ * restriction in place from JSP chipset. Hence create SMI Handler to
  * perform CSME function disabling logic during SMM mode.
  */
 void smihandler_soc_at_finalize(void)
 {
-	const struct soc_intel_tigerlake_config *config;
+	const struct soc_intel_jasperlake_config *config;
 
 	config = config_of_soc();
 
diff --git a/src/soc/intel/jasperlake/spi.c b/src/soc/intel/jasperlake/spi.c
index 5270616af6..9f3f44a227 100644
--- a/src/soc/intel/jasperlake/spi.c
+++ b/src/soc/intel/jasperlake/spi.c
@@ -13,12 +13,6 @@
  * GNU General Public License for more details.
  */
 
-/*
- * This file is created based on Intel Tiger Lake Processor PCH Datasheet
- * Document number: 575857
- * Chapter number: 7
- */
-
 #include <intelblocks/spi.h>
 #include <soc/pci_devs.h>
 
diff --git a/src/soc/intel/jasperlake/systemagent.c b/src/soc/intel/jasperlake/systemagent.c
index fb0ce118aa..92777bfe5b 100644
--- a/src/soc/intel/jasperlake/systemagent.c
+++ b/src/soc/intel/jasperlake/systemagent.c
@@ -12,12 +12,6 @@
  * GNU General Public License for more details.
  */
 
-/*
- * This file is created based on Intel Tiger Lake Processor SA Datasheet
- * Document number: 571131
- * Chapter number: 3
- */
-
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ops.h>
diff --git a/src/soc/intel/jasperlake/uart.c b/src/soc/intel/jasperlake/uart.c
index 03b4469a98..50849560ac 100644
--- a/src/soc/intel/jasperlake/uart.c
+++ b/src/soc/intel/jasperlake/uart.c
@@ -12,12 +12,6 @@
  * GNU General Public License for more details.
  */
 
-/*
- * This file is created based on Intel Tiger Lake Processor PCH Datasheet
- * Document number: 575857
- * Chapter number: 9
- */
-
 #include <console/console.h>
 #include <device/pci_def.h>
 #include <intelblocks/gpio.h>
author	Aamir Bohra <aamir.bohra@intel.com>	2020-03-25 13:20:34 +0530
committer	Subrata Banik <subrata.banik@intel.com>	2020-03-28 14:08:23 +0000
commit	512b77abb582e6c2566d3873b273dd32731e7bae (patch)
tree	8807f78791588d361bd1cef00e11f6619203c713
parent	dd7acaad27e4f99f025df7f06d71dbb49d0e399b (diff)
download	coreboot-512b77abb582e6c2566d3873b273dd32731e7bae.tar.xz