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| author | Furquan Shaikh <furquan@chromium.org> | 2016-10-28 14:55:46 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2016-10-29 00:23:09 +0200 |
| commit | 566feddeceb421ba6480bcee94f87bc4c95c6196 (patch) | |
| tree | 1dc6f059c58d7f3382e497d9690235856a737732 | |
| parent | 4ef7491b2213555ad71920035b5d08e7798024fb (diff) | |
| download | coreboot-566feddeceb421ba6480bcee94f87bc4c95c6196.tar.xz | |
soc/intel/common: Add reset.c to postcar
ramstage_cache_invalid which was added in
I83fe76957c061f20e9afb308e55923806fda4f93 (review.coreboot.org/#/c/17112)
requires hard_reset to be defined in postcar stage.
BUG=None
BRANCH=None
TEST=Compiles successfully for reef.
Change-Id: I283277c373259e0e2dfe72e3c889ceea012544f2
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17182
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
| -rw-r--r-- | src/soc/intel/common/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index 888c657f3e..38903a0ae7 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -15,6 +15,7 @@ romstage-y += util.c romstage-$(CONFIG_MMA) += mma.c postcar-y += util.c +postcar-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c ramstage-y += hda_verb.c ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c |