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| author | Maxim Polyakov <max.senia.poliak@gmail.com> | 2020-03-22 14:57:36 +0300 |
|---|---|---|
| committer | Andrey Petrov <andrey.petrov@gmail.com> | 2020-04-07 18:19:13 +0000 |
| commit | 5b06ffea5691562eb275d4cce809d6419ca75765 (patch) | |
| tree | 0a18ebeb827db69d736a6f3fe2380e58b4a75e0a | |
| parent | ce2399a4461a3e52c992f1cbaf3a66816c2495c0 (diff) | |
| download | coreboot-5b06ffea5691562eb275d4cce809d6419ca75765.tar.xz | |
soc/xeon_sp: add configs to use common/gpio diver
Allow the use of the common/gpio driver to create Lewisburg PCH pad
configurations for server motherboards with Skylake-SP processors.
This patch should only be applied after adding Lewisburg PCH definitions
to the soc/intel/xeon_sp code [1].
[1] https://review.coreboot.org/c/coreboot/+/39425
Change-Id: I4a8e83cad0729bbbb50ba5a2b336f6cf7c1eca13
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39428
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
| -rw-r--r-- | src/soc/intel/xeon_sp/Kconfig | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 468cb44c27..b10c7bee10 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -61,6 +61,10 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_RTC select SOC_INTEL_COMMON_BLOCK_SPI select SOC_INTEL_COMMON_BLOCK_FAST_SPI + select SOC_INTEL_COMMON_BLOCK_GPIO + select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT + select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS + select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL select SOC_INTEL_COMMON_BLOCK_PCR select TSC_MONOTONIC_TIMER select UDELAY_TSC |