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authorMarshall Dawson <marshalldawson3rd@gmail.com>2017-10-04 15:10:00 -0600
committerAaron Durbin <adurbin@chromium.org>2017-11-10 19:15:38 +0000
commit6139a5c6ad369cebd16cd8a9c800c30121c7873b (patch)
tree1dca6f056c8c35dd76d24a86755f4219d7a1245b
parent77fee09509807f17d2d8a638b3e72cacb5bcdbc4 (diff)
downloadcoreboot-6139a5c6ad369cebd16cd8a9c800c30121c7873b.tar.xz
arch/x86: Add common AMD ACPI hardware definitions
Match the corresonding Intel definitions for the ACPI register definitions. Change-Id: Ib804f4544d04fe08fefa493d75e0375de7cf9348 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21883 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
-rw-r--r--src/acpi/Kconfig8
-rw-r--r--src/arch/x86/include/arch/acpi.h32
2 files changed, 28 insertions, 12 deletions
diff --git a/src/acpi/Kconfig b/src/acpi/Kconfig
index 80276f5889..72cfff50c1 100644
--- a/src/acpi/Kconfig
+++ b/src/acpi/Kconfig
@@ -8,5 +8,11 @@ config ACPI_SATA_GENERATOR
config ACPI_INTEL_HARDWARE_SLEEP_VALUES
def_bool n
help
- Provide common definitions for Intel hardware PM1_CNT regiser sleep
+ Provide common definitions for Intel hardware PM1_CNT register sleep
+ values.
+
+config ACPI_AMD_HARDWARE_SLEEP_VALUES
+ def_bool n
+ help
+ Provide common definitions for AMD hardware PM1_CNT register sleep
values.
diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h
index 13e1e9347a..1b239912d7 100644
--- a/src/arch/x86/include/arch/acpi.h
+++ b/src/arch/x86/include/arch/acpi.h
@@ -28,19 +28,28 @@
#define HIGH_MEMORY_SAVE (CONFIG_RAMTOP - CONFIG_RAMBASE)
-#if IS_ENABLED(CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES)
/*
* The type and enable fields are common in ACPI, but the
- * values themselves are hardware implementation idefiend.
+ * values themselves are hardware implementation defined.
*/
-#define SLP_EN (1 << 13)
-#define SLP_TYP_SHIFT 10
-#define SLP_TYP (7 << SLP_TYP_SHIFT)
-#define SLP_TYP_S0 0
-#define SLP_TYP_S1 1
-#define SLP_TYP_S3 5
-#define SLP_TYP_S4 6
-#define SLP_TYP_S5 7
+#if IS_ENABLED(CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES)
+ #define SLP_EN (1 << 13)
+ #define SLP_TYP_SHIFT 10
+ #define SLP_TYP (7 << SLP_TYP_SHIFT)
+ #define SLP_TYP_S0 0
+ #define SLP_TYP_S1 1
+ #define SLP_TYP_S3 5
+ #define SLP_TYP_S4 6
+ #define SLP_TYP_S5 7
+#elif IS_ENABLED(CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES)
+ #define SLP_EN (1 << 13)
+ #define SLP_TYP_SHIFT 10
+ #define SLP_TYP (7 << SLP_TYP_SHIFT)
+ #define SLP_TYP_S0 0
+ #define SLP_TYP_S1 1
+ #define SLP_TYP_S3 3
+ #define SLP_TYP_S4 4
+ #define SLP_TYP_S5 5
#endif
#if !defined(__ASSEMBLER__) && !defined(__ACPI__) && !defined(__ROMCC__)
@@ -700,7 +709,8 @@ enum {
ACPI_S5,
};
-#if IS_ENABLED(CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES)
+#if IS_ENABLED(CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES) \
+ || IS_ENABLED(CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES)
/* Given the provided PM1 control register return the ACPI sleep type. */
static inline int acpi_sleep_from_pm1(uint32_t pm1_cnt)
{