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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2019-05-05 16:35:55 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-05-07 15:52:07 +0000 |
| commit | 66b35bad88807fa18a5ade87283fdb5ffef538f0 (patch) | |
| tree | a1d57fe4d780a3dd0687ba525127e9eb0a738745 | |
| parent | 1bc7b6e1350c4ba8eee10a859d10150b15b7b7e9 (diff) | |
| download | coreboot-66b35bad88807fa18a5ade87283fdb5ffef538f0.tar.xz | |
mb/lenovo/x60: Use system_reset()
Change-Id: I4515d8d14629741f3bf49e9459d7d57c18d321ce
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Nico Huber <nico.h@gmx.de>
| -rw-r--r-- | src/mainboard/lenovo/x60/romstage.c | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 95192f733b..ea93707ce9 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -19,6 +19,7 @@ #include <stdint.h> #include <arch/io.h> +#include <cf9_reset.h> #include <device/pnp_ops.h> #include <device/pci_ops.h> #include <device/pci_def.h> @@ -28,7 +29,6 @@ #include <console/console.h> #include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> -#include <halt.h> #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h> @@ -198,8 +198,7 @@ void mainboard_romstage_entry(unsigned long bist) if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "Soft reset detected, rebooting properly.\n"); - outb(0x6, 0xcf9); - halt(); + system_reset(); } /* Perform some early chipset initialization required |