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| author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-06-08 12:47:07 -0700 |
|---|---|---|
| committer | Leroy P Leahy <leroy.p.leahy@intel.com> | 2016-06-09 22:45:51 +0200 |
| commit | 6735871531301f56384376c54d88bbc75b660e74 (patch) | |
| tree | 46542a12ce940f5939d4f9baab179cd6caab1c3b | |
| parent | de4b09fa26f37396ceaaa27d6ca8a038364f1e52 (diff) | |
| download | coreboot-6735871531301f56384376c54d88bbc75b660e74.tar.xz | |
mainboard: Support ROM_SIZE > 16 MiB
Support ROM_SIZE greater than 16 MiB. Work around SMBIOS rom size
limitation of 16 MiB by specifying 16 MiB as the ROM size.
TEST=Build and run on neoncity
Change-Id: I3f464599cd8a1b6482db8b9deab03126c8b92128
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15108
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
| -rw-r--r-- | src/arch/x86/smbios.c | 8 | ||||
| -rw-r--r-- | src/mainboard/Kconfig | 20 |
2 files changed, 27 insertions, 1 deletions
diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 7b6dda18fa..5784beb088 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -292,7 +292,13 @@ static int smbios_write_type0(unsigned long *current, int handle) #endif #endif /* CONFIG_CHROMEOS */ - t->bios_rom_size = (CONFIG_ROM_SIZE / 65535) - 1; + /* As a work around to prevent a compiler error, temporarily specify + * 16 MiB flash sizes when ROM size >= 16 MiB. An update is necessary + * once the SMBIOS specification addresses ROM sizes > 16 MiB. + */ + uint32_t rom_size = CONFIG_ROM_SIZE; + rom_size = MIN(CONFIG_ROM_SIZE, 16 * MiB); + t->bios_rom_size = (rom_size / 65535) - 1; t->system_bios_major_release = 4; t->bios_characteristics = diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index ab8ee26a9d..24c1fe3777 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -28,6 +28,10 @@ config BOARD_ROMSIZE_KB_12288 bool config BOARD_ROMSIZE_KB_16384 bool +config BOARD_ROMSIZE_KB_32768 + bool +config BOARD_ROMSIZE_KB_65536 + bool # TODO: No help text possible for choice fields? choice @@ -42,6 +46,8 @@ choice default COREBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192 default COREBOOT_ROMSIZE_KB_12288 if BOARD_ROMSIZE_KB_12288 default COREBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384 + default COREBOOT_ROMSIZE_KB_32768 if BOARD_ROMSIZE_KB_32768 + default COREBOOT_ROMSIZE_KB_65536 if BOARD_ROMSIZE_KB_65536 help Select the size of the ROM chip you intend to flash coreboot on. @@ -98,6 +104,16 @@ config COREBOOT_ROMSIZE_KB_16384 help Choose this option if you have a 16384 KB (16 MB) ROM chip. +config COREBOOT_ROMSIZE_KB_32768 + bool "32768 KB (32 MB)" + help + Choose this option if you have a 32768 KB (32 MB) ROM chip. + +config COREBOOT_ROMSIZE_KB_65536 + bool "65536 KB (64 MB)" + help + Choose this option if you have a 65536 KB (64 MB) ROM chip. + endchoice # Map the config names to an integer (KB). @@ -113,6 +129,8 @@ config COREBOOT_ROMSIZE_KB default 8192 if COREBOOT_ROMSIZE_KB_8192 default 12288 if COREBOOT_ROMSIZE_KB_12288 default 16384 if COREBOOT_ROMSIZE_KB_16384 + default 32768 if COREBOOT_ROMSIZE_KB_32768 + default 65536 if COREBOOT_ROMSIZE_KB_65536 # Map the config names to a hex value (bytes). config ROM_SIZE @@ -127,6 +145,8 @@ config ROM_SIZE default 0x800000 if COREBOOT_ROMSIZE_KB_8192 default 0xc00000 if COREBOOT_ROMSIZE_KB_12288 default 0x1000000 if COREBOOT_ROMSIZE_KB_16384 + default 0x2000000 if COREBOOT_ROMSIZE_KB_32768 + default 0x4000000 if COREBOOT_ROMSIZE_KB_65536 config ENABLE_POWER_BUTTON bool "Enable the power button" if POWER_BUTTON_IS_OPTIONAL |