soc/intel/apollolake: Add iosstate macros for GPIO

IO Standby State (IOSSTATE): The I/O Standby State defines
which state the pad should be parked in when the I/O is in a
standby state. Iosstate set to 15 means IO-Standby is ignored
for this pin (same as functional mode), So that pin keeps on
functioning in S3/S0iX.

Change-Id: Ie51ff86a2ea63fa6535407fcc2df7a137ee43e8b
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Signed-off-by: Shankar, Vaibhav <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/15776
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

3 files changed, 54 insertions, 8 deletions

diff --git a/src/soc/intel/apollolake/gpio.c b/src/soc/intel/apollolake/gpio.c
index a3ffb3de0f..2d325255e7 100644
--- a/src/soc/intel/apollolake/gpio.c
+++ b/src/soc/intel/apollolake/gpio.c
@@ -85,10 +85,19 @@ static void gpio_configure_itss(const struct pad_config *cfg,
 
 void gpio_configure_pad(const struct pad_config *cfg)
 {
+	uint32_t dw1;
 	const struct pad_community *comm = gpio_get_community(cfg->pad);
 	uint16_t config_offset = PAD_CFG_OFFSET(cfg->pad - comm->first_pad);
+
+	/* Iostandby bits are tentatively stored in [3:0] bits (RO) of config1.
+	 * dw1 is used to extract the bits of Iostandby.
+	 * This is done to preserve config1 size as unit16 in gpio.h.
+	 */
+	dw1 = cfg->config1 & ~PAD_CFG1_IOSSTATE_MASK;
+	dw1 |= (cfg->config1 & PAD_CFG1_IOSSTATE_MASK) << PAD_CFG1_IOSSTATE_SHIFT;
+
 	iosf_write(comm->port, config_offset, cfg->config0);
-	iosf_write(comm->port, config_offset + sizeof(uint32_t), cfg->config1);
+	iosf_write(comm->port, config_offset + sizeof(uint32_t), dw1);
 
 	gpio_configure_itss(cfg, comm->port, config_offset);
 }
diff --git a/src/soc/intel/apollolake/include/soc/gpio.h b/src/soc/intel/apollolake/include/soc/gpio.h
index 1ebac2dabc..fc2401d165 100644
--- a/src/soc/intel/apollolake/include/soc/gpio.h
+++ b/src/soc/intel/apollolake/include/soc/gpio.h
@@ -28,6 +28,7 @@ typedef uint32_t gpio_t;
 #define PAD_FUNC(value)		PAD_CFG0_MODE_##value
 #define PAD_RESET(value)	PAD_CFG0_RESET_##value
 #define PAD_PULL(value)		PAD_CFG1_PULL_##value
+#define PAD_IOSSTATE(value)	PAD_CFG1_IOSSTATE_##value
 #define PAD_IRQ_CFG(route, trig, inv) \
 				(PAD_CFG0_ROUTE_##route | \
 				PAD_CFG0_TRIG_##trig | \
@@ -42,19 +43,25 @@ typedef uint32_t gpio_t;
 
 /* Native function configuration */
 #define PAD_CFG_NF(pad, pull, rst, func) \
-	_PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull))
+	_PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \
+		PAD_IOSSTATE(TxLASTRxE))
+
+/* Native function configuration for standby state */
+#define PAD_CFG_NF_IOSSTATE(pad, pull, rst, func, iosstate) \
+	_PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \
+		PAD_IOSSTATE(iosstate))
 
 /* General purpose output, no pullup/down. */
 #define PAD_CFG_GPO(pad, val, rst)	\
 	_PAD_CFG_STRUCT(pad,		\
 		PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \
-		PAD_PULL(NONE))
+		PAD_PULL(NONE) | PAD_IOSSTATE(TxLASTRxE))
 
 /* General purpose input */
 #define PAD_CFG_GPI(pad, pull, rst) \
 	_PAD_CFG_STRUCT(pad,		\
 		PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \
-		PAD_PULL(pull))
+		PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE))
 
 /* No Connect configuration for unused pad.
  * NC should be GPI with Term as PU20K, PD20K, NONE depending upon default Term
@@ -65,7 +72,8 @@ typedef uint32_t gpio_t;
 #define PAD_CFG_GPI_APIC(pad, pull, rst, trig, inv) \
 	_PAD_CFG_STRUCT(pad,		\
 		PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
-		PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull))
+		PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \
+		PAD_IOSSTATE(TxLASTRxE))
 
 /*
  * The following APIC macros assume the APIC will handle the filtering
@@ -82,7 +90,8 @@ typedef uint32_t gpio_t;
 #define PAD_CFG_GPI_SMI(pad, pull, rst, trig, inv) \
 	_PAD_CFG_STRUCT(pad,		\
 		PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
-		PAD_IRQ_CFG(SMI, trig, inv), PAD_PULL(pull))
+		PAD_IRQ_CFG(SMI, trig, inv), PAD_PULL(pull) | \
+		PAD_IOSSTATE(TxLASTRxE))
 
 #define PAD_CFG_GPI_SMI_LOW(pad, pull, rst, trig) \
 	PAD_CFG_GPI_SMI(pad, pull, rst, trig, INVERT)
@@ -94,7 +103,8 @@ typedef uint32_t gpio_t;
 #define PAD_CFG_GPI_SCI(pad, pull, rst, trig, inv) \
 	_PAD_CFG_STRUCT(pad,		\
 		PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
-		PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull))
+		PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \
+		PAD_IOSSTATE(TxLASTRxE))
 
 #define PAD_CFG_GPI_SCI_LOW(pad, pull, rst, trig) \
 	PAD_CFG_GPI_SCI(pad, pull, rst, trig, INVERT)
@@ -106,7 +116,8 @@ typedef uint32_t gpio_t;
 #define PAD_CFG_GPI_NMI(pad, pull, rst, trig, inv) \
 	_PAD_CFG_STRUCT(pad,		\
 		PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
-		PAD_IRQ_CFG(NMI, trig, inv), PAD_PULL(pull))
+		PAD_IRQ_CFG(NMI, trig, inv), PAD_PULL(pull) | \
+		PAD_IOSSTATE(TxLASTRxE))
 
 struct pad_config {
 	uint32_t config0;
diff --git a/src/soc/intel/apollolake/include/soc/gpio_defs.h b/src/soc/intel/apollolake/include/soc/gpio_defs.h
index aa1ce8cf65..0a9fb151ea 100644
--- a/src/soc/intel/apollolake/include/soc/gpio_defs.h
+++ b/src/soc/intel/apollolake/include/soc/gpio_defs.h
@@ -86,6 +86,32 @@
 #define  PAD_CFG1_PULL_UP_20K		(0xc << 10)
 #define  PAD_CFG1_PULL_UP_667		(0xd << 10)
 #define  PAD_CFG1_PULL_NATIVE		(0xf << 10)
+/* Tx enabled driving last value driven, Rx enabled */
+#define PAD_CFG1_IOSSTATE_TxLASTRxE	(0x0 << 0)
+/* Tx enabled driving 0, Rx disabled and Rx driving 0 back to its controller
+ * internally */
+#define PAD_CFG1_IOSSTATE_Tx0RxDCRx0	(0x1 << 0)
+/* Tx enabled driving 0, Rx disabled and Rx driving 1 back to its controller
+ * internally */
+#define PAD_CFG1_IOSSTATE_Tx0RXDCRx1	(0x2 << 0)
+/* Tx enabled driving 1, Rx disabled and Rx driving 0 back to its controller
+ * internally */
+#define PAD_CFG1_IOSSTATE_Tx1RXDCRx0	(0x3 << 0)
+/* Tx enabled driving 1, Rx disabled and Rx driving 1 back to its controller
+ * internally */
+#define PAD_CFG1_IOSSTATE_Tx1RxDCRx1	(0x4 << 0)
+/* Tx enabled driving 0, Rx enabled */
+#define PAD_CFG1_IOSSTATE_Tx0RxE	(0x5 << 0)
+/* Tx enabled driving 1, Rx enabled */
+#define PAD_CFG1_IOSSTATE_Tx1RxE	(0x6 << 0)
+/* Hi-Z, Rx driving 0 back to its controller internally */
+#define PAD_CFG1_IOSSTATE_HIZCRx0	(0x7 << 0)
+/* Hi-Z, Rx driving 1 back to its controller internally */
+#define PAD_CFG1_IOSSTATE_HIZCRx1	(0x8 << 0)
+#define PAD_CFG1_IOSSTATE_TxDRxE	(0x9 << 0) /* Tx disabled, Rx enabled */
+#define PAD_CFG1_IOSSTATE_IGNORE	(0xf << 0) /* Ignore Iostandby */
+#define PAD_CFG1_IOSSTATE_MASK		0xf /* mask to extract Iostandby bits */
+#define PAD_CFG1_IOSSTATE_SHIFT	14 /* set Iostandby bits [17:14] */
 
 #define PAD_CFG_BASE			0x500
 #define PAD_CFG_OFFSET(pad)		(PAD_CFG_BASE + ((pad) * 8))