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authorNico Huber <nico.h@gmx.de>2019-11-17 01:45:50 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-11-18 11:51:26 +0000
commit6b7b016b6006feb22b48a44b25fd71f1f39ad9cb (patch)
treeec2b51076272ba80233d15c5b6db0686a6c23e3b
parent25128a79970bc9756ad33e1f1740e11321d1ff40 (diff)
downloadcoreboot-6b7b016b6006feb22b48a44b25fd71f1f39ad9cb.tar.xz
mb/sapphire/pureplatinumh61: Don't write BUC and beyond
The BUC register is actually only 8 bits wide and setting bit 5 (disabling GbE) is already done by generic code. Change-Id: I729a2a28f4b0d94eddd070dc89b7341ac0c35e4a Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
-rw-r--r--src/mainboard/sapphire/pureplatinumh61/early_init.c5
1 files changed, 0 insertions, 5 deletions
diff --git a/src/mainboard/sapphire/pureplatinumh61/early_init.c b/src/mainboard/sapphire/pureplatinumh61/early_init.c
index be665617a4..9a1b6856ff 100644
--- a/src/mainboard/sapphire/pureplatinumh61/early_init.c
+++ b/src/mainboard/sapphire/pureplatinumh61/early_init.c
@@ -26,11 +26,6 @@ void mainboard_pch_lpc_setup(void)
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x00010000);
}
-void mainboard_late_rcba_config(void)
-{
- /* Disable devices. */
- RCBA32(0x3414) = 0x00000020;
-}
const struct southbridge_usb_port mainboard_usb_ports[] = {
{ 1, 0, 0 },
{ 1, 0, 0 },