diff options
| author | Shelley Chen <shchen@chromium.org> | 2017-05-03 12:42:20 -0700 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2017-05-17 04:09:19 +0200 |
| commit | 6f1bfaba8ce27851984e0b495917ef2b8b4c31b3 (patch) | |
| tree | c309bf969d54b80e305d53ddebd5d35f39572f81 | |
| parent | d84c8f8601d1f8fad006cb2844caadf8dbd69962 (diff) | |
| download | coreboot-6f1bfaba8ce27851984e0b495917ef2b8b4c31b3.tar.xz | |
google/fizz: Configure SATAXPCIe GPIOs to use native function
BUG=b:37486021, b:35775024
BRANCH=None
TEST=reboot and ensure that device detects SSD
Change-Id: I4a85b9f3ba1d0a4c0a753420e166d3353417a1d1
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/19554
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Shelley Chen <shchen@google.com>
| -rw-r--r-- | src/mainboard/google/fizz/gpio.h | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/mainboard/google/fizz/gpio.h b/src/mainboard/google/fizz/gpio.h index 1cd9d53f8e..0950c76dbd 100644 --- a/src/mainboard/google/fizz/gpio.h +++ b/src/mainboard/google/fizz/gpio.h @@ -143,9 +143,10 @@ static const struct pad_config gpio_table[] = { /* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), /* H1_PCH_INT_ODL */ -/* SATAXPCIE1 */ PAD_CFG_GPI(GPP_E1, NONE, DEEP), /* MB_PCIE_SATA#_DET */ -/* SATAXPCIE2 */ PAD_CFG_GPI(GPP_E2, 20K_PU, - DEEP), /* DB_PCIE_SATA#_DET */ +/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, + NF1), /* MB_PCIE_SATA#_DET */ +/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, 20K_PU, DEEP, + NF1), /* DB_PCIE_SATA#_DET */ /* CPU_GP0 */ PAD_CFG_NC(GPP_E3), /* SATA_DEVSLP0 */ PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1), /* DEVSLP0_MB */ /* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1_DB */ |