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authorAngel Pons <th3fanbus@gmail.com>2020-09-25 00:23:20 +0200
committerMichael Niewöhner <foss@mniewoehner.de>2020-10-24 14:03:54 +0000
commit72f4dda6b7d1de5eef1df1d32be4595067c4a15d (patch)
treebaaeb4f0353831bead527ff08cfd83e58814bd14
parentd3318cfe498bf53d8ce7d1cd55afad4a93705216 (diff)
downloadcoreboot-72f4dda6b7d1de5eef1df1d32be4595067c4a15d.tar.xz
sb/intel/lynxpoint/pcie: Fix clock gating routine
The use of `1 < 5` as a bit mask was obviously a typo. Correct it as `1 << 5` to match what Intel doc #493816 (Lynx Point PCH BWG) states. Change-Id: I85734a68a42ec65b124d68514039a1dda7946adc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45713 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/southbridge/intel/lynxpoint/pcie.c3
1 files changed, 1 insertions, 2 deletions
diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c
index 112c9d3fa3..4a245b1899 100644
--- a/src/southbridge/intel/lynxpoint/pcie.c
+++ b/src/southbridge/intel/lynxpoint/pcie.c
@@ -283,8 +283,7 @@ static void pcie_enable_clock_gating(void)
/* Update PECR1 register. */
pci_or_config8(dev, 0xe8, 1);
- /* FIXME: Are we supposed to update this register with a constant boolean? */
- pci_update_config8(dev, 0x324, ~(1 << 5), (1 < 5));
+ pci_or_config8(dev, 0x324, 1 << 5);
/* Per-Port CLKREQ# handling. */
if (is_lp && gpio_is_native(18 + rp - 1))