[WIP] mb/hp: Add EliteBook 820 G2

Currently it boots to SeaBIOS.

Change-Id: Id8b3b7f735460c5e76a2dc9ab2d10154e6606ad6
Signed-off-by: Iru Cai <mytbk920423@gmail.com>

15 files changed, 444 insertions, 0 deletions

diff --git a/src/mainboard/hp/820g2/Kconfig b/src/mainboard/hp/820g2/Kconfig
new file mode 100644
index 0000000000..f617551d43
--- /dev/null
+++ b/src/mainboard/hp/820g2/Kconfig
@@ -0,0 +1,34 @@
+if BOARD_HP_820_G2
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_16384
+	select EC_ACPI
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select INTEL_INT15
+	select MAINBOARD_HAS_LIBGFXINIT # FIXME: check this
+	select SOC_INTEL_BROADWELL
+	select SYSTEM_TYPE_LAPTOP
+
+config MAINBOARD_DIR
+	string
+	default "hp/820g2"
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "EliteBook 820 G2"
+
+config VGA_BIOS_FILE
+	string
+	default "pci8086,1616.rom"
+
+config VGA_BIOS_ID
+	string
+	default "8086,1616"
+
+config MAX_CPUS
+	int
+	default 8
+
+endif
diff --git a/src/mainboard/hp/820g2/Kconfig.name b/src/mainboard/hp/820g2/Kconfig.name
new file mode 100644
index 0000000000..3fcf1a12c1
--- /dev/null
+++ b/src/mainboard/hp/820g2/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_HP_820_G2
+	bool "EliteBook 820 G2"
diff --git a/src/mainboard/hp/820g2/Makefile.inc b/src/mainboard/hp/820g2/Makefile.inc
new file mode 100644
index 0000000000..2543ee70da
--- /dev/null
+++ b/src/mainboard/hp/820g2/Makefile.inc
@@ -0,0 +1,4 @@
+romstage-y += gpio.c
+romstage-y += pei_data.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+ramstage-y += pei_data.c
diff --git a/src/mainboard/hp/820g2/acpi/ec.asl b/src/mainboard/hp/820g2/acpi/ec.asl
new file mode 100644
index 0000000000..d39c59ab2e
--- /dev/null
+++ b/src/mainboard/hp/820g2/acpi/ec.asl
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Device(EC)
+{
+	Name (_HID, EISAID("PNP0C09"))
+	Name (_UID, 0)
+	Name (_GPE, 6)
+/* FIXME: EC support */
+}
diff --git a/src/mainboard/hp/820g2/acpi/superio.asl b/src/mainboard/hp/820g2/acpi/superio.asl
new file mode 100644
index 0000000000..55b1db5b11
--- /dev/null
+++ b/src/mainboard/hp/820g2/acpi/superio.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/pc80/pc/ps2_controller.asl>
diff --git a/src/mainboard/hp/820g2/acpi_tables.c b/src/mainboard/hp/820g2/acpi_tables.c
new file mode 100644
index 0000000000..ca6f64b089
--- /dev/null
+++ b/src/mainboard/hp/820g2/acpi_tables.c
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
+#include <arch/ioapic.h>
+#include <soc/acpi.h>
+#include <soc/nvs.h>
+
+void acpi_create_gnvs(struct global_nvs *gnvs)
+{
+	acpi_init_gnvs(gnvs);
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+	/* Local APICs */
+	current = acpi_create_madt_lapics(current);
+
+	/* IOAPIC */
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+				2, IO_APIC_ADDR, 0);
+
+	return acpi_madt_irq_overrides(current);
+}
diff --git a/src/mainboard/hp/820g2/board_info.txt b/src/mainboard/hp/820g2/board_info.txt
new file mode 100644
index 0000000000..db677c6572
--- /dev/null
+++ b/src/mainboard/hp/820g2/board_info.txt
@@ -0,0 +1,2 @@
+Category: laptop
+FIXME: put ROM package, ROM socketed, ROM protocol, Flashrom support, Release year
diff --git a/src/mainboard/hp/820g2/devicetree.cb b/src/mainboard/hp/820g2/devicetree.cb
new file mode 100644
index 0000000000..57cf333fbc
--- /dev/null
+++ b/src/mainboard/hp/820g2/devicetree.cb
@@ -0,0 +1,119 @@
+chip soc/intel/broadwell # FIXME: check these values
+	register "alt_gp_smi_en" = "0"
+	register "gen1_dec" = "0x007c0201"
+	register "gen2_dec" = "0x000c0101"
+	register "gen3_dec" = "0x00000000"
+	register "gen4_dec" = "0x000402e9"
+	register "gfx" = "GMA_STATIC_DISPLAYS(0)"
+	register "gpe0_en_1" = "0"
+	register "gpe0_en_2" = "0"
+	register "gpe0_en_3" = "0"
+	register "gpe0_en_4" = "0"
+	register "gpu_dp_b_hotplug" = "4"
+	register "gpu_dp_c_hotplug" = "4"
+	register "gpu_dp_d_hotplug" = "4"
+	register "gpu_panel_power_backlight_off_delay" = "1"
+	register "gpu_panel_power_backlight_on_delay" = "1"
+	register "gpu_panel_power_cycle_delay" = "6"
+	register "gpu_panel_power_down_delay" = "500"
+	register "gpu_panel_power_up_delay" = "2000"
+	register "gpu_pch_backlight_pwm_hz" = "200"
+	register "pcie_port_coalesce" = "1"
+	register "pcie_port_force_aspm" = "0"
+	register "sata_devslp_disable" = "0"
+	register "sata_devslp_mux" = "0"
+	register "sata_port0_gen3_dtle" = "0x0"
+	register "sata_port0_gen3_tx" = "0x0"
+	register "sata_port1_gen3_dtle" = "0x0"
+	register "sata_port1_gen3_tx" = "0x0"
+	register "sata_port2_gen3_dtle" = "0x0"
+	register "sata_port2_gen3_tx" = "0x0"
+	register "sata_port3_gen3_dtle" = "0x0"
+	register "sata_port3_gen3_tx" = "0x0"
+	register "sata_port_map" = "0xa"
+	register "sio_acpi_mode" = "0"
+	register "sio_i2c0_voltage" = "0"
+	register "sio_i2c1_voltage" = "0"
+	device cpu_cluster 0x0 on
+		device lapic 0x0 on
+		end
+	end
+	device domain 0x0 on
+		device pci 00.0 on # Host bridge
+			subsystemid 0x103c 0x225a
+		end
+		device pci 02.0 on # Internal graphics VGA controller
+			subsystemid 0x103c 0x225a
+		end
+		device pci 03.0 on # Mini-HD audio
+			subsystemid 0x103c 0x225a
+		end
+		device pci 13.0 off # Smart Sound Audio DSP
+		end
+		device pci 14.0 on # xHCI Controller
+			subsystemid 0x103c 0x225a
+		end
+		device pci 15.0 off # Serial I/O DMA
+		end
+		device pci 15.1 off # I2C0
+		end
+		device pci 15.2 off # I2C1
+		end
+		device pci 15.3 off # GSPI0
+		end
+		device pci 15.4 off # GSPI1
+		end
+		device pci 15.5 off # UART0
+		end
+		device pci 15.6 off # UART1
+		end
+		device pci 16.0 on # Management Engine Interface 1
+			subsystemid 0x103c 0x225a
+		end
+		device pci 16.1 off # Management Engine Interface 2
+		end
+		device pci 16.2 off # Management Engine IDE-R
+		end
+		device pci 16.3 off # Management Engine KT
+		end
+		device pci 17.0 off # SDIO
+		end
+		device pci 19.0 on # Intel Gigabit Ethernet Unsupported PCI device 8086:15a2
+			subsystemid 0x103c 0x225a
+		end
+		device pci 1b.0 on # High Definition Audio
+			subsystemid 0x103c 0x225a
+		end
+		device pci 1c.0 on # PCIe Port #1
+			subsystemid 0x103c 0x225a
+		end
+		device pci 1c.1 on # PCIe Port #2
+			subsystemid 0x103c 0x225a
+		end
+		device pci 1c.2 off # PCIe Port #3
+		end
+		device pci 1c.3 on # PCIe Port #4
+			subsystemid 0x103c 0x225a
+		end
+		device pci 1c.4 off # PCIe Port #5
+		end
+		device pci 1c.5 off # PCIe Port #6
+		end
+		device pci 1d.0 on # USB2 EHCI #1
+			subsystemid 0x103c 0x225a
+		end
+		device pci 1e.0 off # PCI bridge
+		end
+		device pci 1f.0 on # LPC bridge
+			subsystemid 0x103c 0x225a
+		end
+		device pci 1f.2 on # SATA Controller (AHCI)
+			subsystemid 0x103c 0x225a
+		end
+		device pci 1f.3 on # SMBus
+			subsystemid 0x103c 0x225a
+		end
+		device pci 1f.6 off # Thermal
+		end
+	end
+end
diff --git a/src/mainboard/hp/820g2/dsdt.asl b/src/mainboard/hp/820g2/dsdt.asl
new file mode 100644
index 0000000000..666115dea6
--- /dev/null
+++ b/src/mainboard/hp/820g2/dsdt.asl
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+
+#include <acpi/acpi.h>
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20141018	/* OEM revision */
+)
+{
+	#include <soc/intel/broadwell/acpi/platform.asl>
+	#include <soc/intel/broadwell/acpi/globalnvs.asl>
+	#include <cpu/intel/common/acpi/cpu.asl>
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+
+	Device (\_SB.PCI0)
+	{
+		#include <soc/intel/broadwell/acpi/systemagent.asl>
+		#include <soc/intel/broadwell/acpi/pch.asl>
+	}
+}
diff --git a/src/mainboard/hp/820g2/gma-mainboard.ads b/src/mainboard/hp/820g2/gma-mainboard.ads
new file mode 100644
index 0000000000..7b900609b5
--- /dev/null
+++ b/src/mainboard/hp/820g2/gma-mainboard.ads
@@ -0,0 +1,19 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+   -- FIXME: check this
+   ports : constant Port_List :=
+     (DP1,
+      DP2,
+      HDMI1,
+      HDMI2,
+      eDP);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/hp/820g2/gpio.c b/src/mainboard/hp/820g2/gpio.c
new file mode 100644
index 0000000000..b4ef103bac
--- /dev/null
+++ b/src/mainboard/hp/820g2/gpio.c
@@ -0,0 +1,108 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/gpio.h>
+
+const struct gpio_config mainboard_gpio_config[] = {
+	[0] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
+	[1] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL },
+	[2] = PCH_GPIO_OUT_LOW,
+	[3] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL },
+	[4] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL },
+	[5] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL },
+	[6] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL },
+	[7] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL },
+	[8] = PCH_GPIO_OUT_HIGH,
+	[9] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
+	[10] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
+	[11] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
+	[12] = PCH_GPIO_NATIVE,
+	[13] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL },
+	[14] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
+	[15] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
+	[16] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL,
+		 .route = GPIO_ROUTE_SMI },
+	[17] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
+	[18] = PCH_GPIO_OUT_HIGH,
+	[19] = PCH_GPIO_NATIVE,
+	[20] = PCH_GPIO_NATIVE,
+	[21] = PCH_GPIO_NATIVE,
+	[22] = PCH_GPIO_NATIVE,
+	[23] = PCH_GPIO_NATIVE,
+	[24] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL,
+		 .reset = GPIO_RESET_RSMRST },
+	[25] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
+	[26] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
+	[27] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL },
+	[28] = PCH_GPIO_OUT_HIGH,
+	[29] = PCH_GPIO_OUT_HIGH,
+	[30] = PCH_GPIO_NATIVE,
+	[31] = PCH_GPIO_NATIVE,
+	[32] = PCH_GPIO_NATIVE,
+	[33] = PCH_GPIO_NATIVE,
+	[34] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
+	[35] = PCH_GPIO_NATIVE,
+	[36] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL,
+		 .route = GPIO_ROUTE_SMI },
+	[37] = PCH_GPIO_NATIVE,
+	[38] = PCH_GPIO_NATIVE,
+	[39] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL,
+		 .route = GPIO_ROUTE_SMI },
+	[40] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL,
+		 .route = GPIO_ROUTE_SMI },
+	[41] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL },
+	[42] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL },
+	[43] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
+	[44] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
+	[45] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL },
+	[46] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
+	[47] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
+	[48] = PCH_GPIO_OUT_HIGH,
+	[49] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
+	[50] = PCH_GPIO_OUT_HIGH,
+	[51] = PCH_GPIO_OUT_HIGH,
+	[52] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
+	[53] = PCH_GPIO_OUT_HIGH,
+	[54] = PCH_GPIO_OUT_HIGH,
+	[55] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, .owner = GPIO_OWNER_GPIO,
+		 .irqen = GPIO_IRQ_ENABLE, .pirq = GPIO_PIRQ_APIC_ROUTE },
+	[56] = PCH_GPIO_OUT_HIGH,
+	[57] = PCH_GPIO_OUT_LOW,
+	[58] = PCH_GPIO_OUT_HIGH,
+	[59] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
+	[60] = PCH_GPIO_OUT_HIGH,
+	[61] = PCH_GPIO_OUT_LOW,
+	[62] = PCH_GPIO_NATIVE,
+	[63] = PCH_GPIO_NATIVE,
+	[64] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL },
+	[65] = PCH_GPIO_OUT_LOW,
+	[66] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
+	[67] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL },
+	[68] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL },
+	[69] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL },
+	[70] = PCH_GPIO_OUT_LOW,
+	[71] = PCH_GPIO_NATIVE,
+	[72] = PCH_GPIO_NATIVE,
+	[73] = PCH_GPIO_NATIVE,
+	[74] = PCH_GPIO_NATIVE,
+	[75] = PCH_GPIO_NATIVE,
+	[76] = PCH_GPIO_NATIVE,
+	[77] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
+	[78] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
+	[79] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
+	[80] = PCH_GPIO_OUT_LOW,
+	[81] = PCH_GPIO_NATIVE,
+	[82] = PCH_GPIO_OUT_HIGH,
+	[83] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
+	[84] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
+	[85] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
+	[86] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
+	[87] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
+	[88] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
+	[89] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
+	[90] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
+	[91] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
+	[92] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
+	[93] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
+	[94] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
+	PCH_GPIO_END
+};
diff --git a/src/mainboard/hp/820g2/hda_verb.c b/src/mainboard/hp/820g2/hda_verb.c
new file mode 100644
index 0000000000..ed96b9fc39
--- /dev/null
+++ b/src/mainboard/hp/820g2/hda_verb.c
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	0x00000000,	/* Codec Vendor / Device ID:  */
+	0x00000000,	/* Subsystem ID */
+	13,		/* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(0, 0x00000000),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x15, 0x0421101f),
+	AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x04a11020),
+	AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1d, 0x40748605),
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/hp/820g2/mainboard.c b/src/mainboard/hp/820g2/mainboard.c
new file mode 100644
index 0000000000..98cc8110cc
--- /dev/null
+++ b/src/mainboard/hp/820g2/mainboard.c
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+#include <drivers/intel/gma/int15.h>
+
+static void mainboard_enable(struct device *dev)
+{
+	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_DEFAULT,
+					GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+}
+
+struct chip_operations mainboard_ops = {
+	.enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/hp/820g2/pei_data.c b/src/mainboard/hp/820g2/pei_data.c
new file mode 100644
index 0000000000..90c45f675c
--- /dev/null
+++ b/src/mainboard/hp/820g2/pei_data.c
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/pei_data.h>
+#include <soc/pei_wrapper.h>
+
+void mainboard_fill_pei_data(struct pei_data *pei_data)
+{
+	pei_data->ec_present = 1;
+
+	/* FIXME: check this */
+	pei_data->dimm_channel0_disabled = 2;
+	pei_data->dimm_channel1_disabled = 2;
+	pei_data->spd_addresses[0] = 0xa0;
+	pei_data->spd_addresses[2] = 0xa4;
+	pei_data->dq_pins_interleaved = 0;
+
+	/* FIXME: USB2 ports */
+	pei_data_usb2_port(pei_data, 0, 0x0080, 1, USB_OC_PIN_SKIP,
+			  USB_PORT_DOCK);
+	pei_data_usb2_port(pei_data, 1, 0x0040, 1, USB_OC_PIN_SKIP,
+			  USB_PORT_BACK_PANEL);
+	pei_data_usb2_port(pei_data, 2, 0x0040, 1, USB_OC_PIN_SKIP,
+			  USB_PORT_BACK_PANEL);
+	pei_data_usb2_port(pei_data, 3, 0x0080, 1, USB_OC_PIN_SKIP,
+			  USB_PORT_MINI_PCIE);
+	pei_data_usb2_port(pei_data, 4, 0x0040, 1, USB_OC_PIN_SKIP,
+			  USB_PORT_BACK_PANEL);
+	pei_data_usb2_port(pei_data, 5, 0x0040, 1, USB_OC_PIN_SKIP,
+			  USB_PORT_BACK_PANEL);
+	pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP,
+			  USB_PORT_BACK_PANEL);
+	pei_data_usb2_port(pei_data, 7, 0x0040, 1, USB_OC_PIN_SKIP,
+			  USB_PORT_BACK_PANEL);
+
+	/* FIXME: USB3 ports */
+	pei_data_usb3_port(pei_data, 0, 1, USB_OC_PIN_SKIP, 0);
+	pei_data_usb3_port(pei_data, 1, 1, USB_OC_PIN_SKIP, 0);
+	pei_data_usb3_port(pei_data, 2, 1, USB_OC_PIN_SKIP, 0);
+	pei_data_usb3_port(pei_data, 3, 1, USB_OC_PIN_SKIP, 0);
+}
diff --git a/src/mainboard/hp/820g2/romstage.c b/src/mainboard/hp/820g2/romstage.c
new file mode 100644
index 0000000000..8fc2f9eaf7
--- /dev/null
+++ b/src/mainboard/hp/820g2/romstage.c
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/pei_data.h>
+#include <soc/pei_wrapper.h>
+#include <soc/romstage.h>
+
+void mainboard_pre_raminit(struct romstage_params *rp)
+{
+	/* Fill out PEI DATA */
+	mainboard_fill_pei_data(&rp->pei_data);
+}
+
+void mainboard_post_raminit(struct romstage_params *rp)
+{
+}