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authorSubrata Banik <subrata.banik@intel.com>2019-05-06 14:17:41 +0530
committerSubrata Banik <subrata.banik@intel.com>2019-05-12 03:10:24 +0000
commit7e893a02c0cc04b8fdcfee0b4dc0ff790bfe40c5 (patch)
tree37dedc9deb63d0961d241a24e08fed15b54d344a
parent7bc9036d160c6235d96e1bed49331696d7fa9a09 (diff)
downloadcoreboot-7e893a02c0cc04b8fdcfee0b4dc0ff790bfe40c5.tar.xz
Kconfig: Create RAMPAYLOAD kconfig
This patch enables coreboot flow to skip ramstage as individual stage to load payload. Instead it is expected to load payload from postcar stage. Change-Id: I839f2d34a93b69ca6bf3de6594e2ad9f66ee7135 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32618 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com>
-rw-r--r--src/Kconfig15
1 files changed, 15 insertions, 0 deletions
diff --git a/src/Kconfig b/src/Kconfig
index b4898bd456..2c9dc4ab7f 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -277,6 +277,21 @@ config BOOTSPLASH_FILE
The path and filename of the file to use as graphical bootsplash
screen. The file format has to be jpg.
+config RAMPAYLOAD
+ bool "Enable coreboot flow without executing ramstage"
+ default n
+ depends on ARCH_X86
+ help
+ If this option is enabled, coreboot flow will skip ramstage
+ loading and execution of ramstage to load payload.
+
+ Instead it is expected to load payload from postcar stage itself.
+
+ In this flow coreboot will perform basic x86 initialization
+ (DRAM resource allocation), MTRR programming,
+ Skip PCI enumeration logic and only allocate BAR for fixed devices
+ (bootable devices, TPM over GSPI).
+
endmenu
menu "Mainboard"