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authorMarc Jones <marcj303@gmail.com>2017-04-26 21:55:03 -0600
committerMarc Jones <marc@marcjonesconsulting.com>2017-05-02 05:17:16 +0200
commit7f2c29b6d6c3d89bc92ad76517821848ed8c23d2 (patch)
treeabc4d6b93d86deb1c26138a9293bed20bd446670
parent6a7ebd4e08b234bdf79e6ffbde8ff2a7a0e57fb7 (diff)
downloadcoreboot-7f2c29b6d6c3d89bc92ad76517821848ed8c23d2.tar.xz
amd/pi/hudson: Add config option for ACPI base
Add a configuration option to assign the binaryPI base address for the ACPI registers. The binaryPI's assignment is determine at build time and no run-time configuration is allowed. Change-Id: Ida17022abfa6faceb0653c2cb87aacce4facef09 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19485 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
-rw-r--r--src/southbridge/amd/pi/hudson/Kconfig9
-rw-r--r--src/southbridge/amd/pi/hudson/hudson.h2
2 files changed, 10 insertions, 1 deletions
diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig
index 233260f026..25dbdb85cd 100644
--- a/src/southbridge/amd/pi/hudson/Kconfig
+++ b/src/southbridge/amd/pi/hudson/Kconfig
@@ -219,6 +219,15 @@ config SERIRQ_CONTINUOUS_MODE
help
Set this option to y for serial IRQ in continuous mode.
Otherwise it is in quiet mode.
+
+config HUDSON_ACPI_IO_BASE
+ hex
+ default 0x400 if CPU_AMD_PI_00670F00_FP4 || CPU_AMD_PI_00670F00_FT4
+ default 0x800
+ help
+ Base address for the ACPI registers.
+ This value must match the hardcoded value of AGESA.
+
endif
config HUDSON_UART
diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h
index e20238f2c3..2ccd485b68 100644
--- a/src/southbridge/amd/pi/hudson/hudson.h
+++ b/src/southbridge/amd/pi/hudson/hudson.h
@@ -51,7 +51,7 @@
#define PM_YANG_SD_FLASH_CTRL 0xE8
#define PM_PCIB_CFG 0xEA
-#define HUDSON_ACPI_IO_BASE 0x800
+#define HUDSON_ACPI_IO_BASE CONFIG_HUDSON_ACPI_IO_BASE
#define ACPI_PM_EVT_BLK (HUDSON_ACPI_IO_BASE + 0x00) /* 4 bytes */
#define ACPI_PM1_CNT_BLK (HUDSON_ACPI_IO_BASE + 0x04) /* 2 bytes */
#define ACPI_PM_TMR_BLK (HUDSON_ACPI_IO_BASE + 0x18) /* 4 bytes */