diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-06-02 13:36:57 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-07 21:48:22 +0000 |
| commit | 7f32df379cd42178a05239b6b1ced435d33d5ffa (patch) | |
| tree | 869abe182c2559e73491a7b9151e4f98d7b175a0 | |
| parent | 93375f270cb09c0a4e4de38f1b6d1a5f8235a6d7 (diff) | |
| download | coreboot-7f32df379cd42178a05239b6b1ced435d33d5ffa.tar.xz | |
sb/intel/bd82x6x: Align some ME functions
This eliminates the differences in the first part of the file.
Change-Id: Ifb7d57da08e02664a28819e65bc8e9697ed38c4c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42009
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/southbridge/intel/bd82x6x/me.c | 6 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/me_8.x.c | 13 |
2 files changed, 11 insertions, 8 deletions
diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index bc0a71e3a7..ebb9db93e5 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -10,10 +10,10 @@ #include <acpi/acpi.h> #include <device/mmio.h> -#include <device/pci_ops.h> -#include <console/console.h> #include <device/device.h> #include <device/pci.h> +#include <device/pci_ops.h> +#include <console/console.h> #include <device/pci_ids.h> #include <device/pci_def.h> #include <string.h> @@ -564,7 +564,7 @@ static int intel_mei_setup(struct device *dev) printk(BIOS_DEBUG, "ME: MEI resource not present!\n"); return -1; } - mei_base_address = (u32*)(uintptr_t)res->base; + mei_base_address = (u32 *)(uintptr_t)res->base; /* Ensure Memory and Bus Master bits are set */ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index f64e29c64a..dd972d2b4e 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -25,12 +25,11 @@ #include "pch.h" #if CONFIG(CHROMEOS) -#include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/gnvs.h> #endif /* Path that the BIOS should take based on ME state */ -static const char *me_bios_path_values[] __unused = { +static const char *me_bios_path_values[] __unused = { [ME_NORMAL_BIOS_PATH] = "Normal", [ME_S3WAKE_BIOS_PATH] = "S3 Wake", [ME_ERROR_BIOS_PATH] = "Error", @@ -38,12 +37,10 @@ static const char *me_bios_path_values[] __unused = { [ME_DISABLE_BIOS_PATH] = "Disable", [ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update", }; -static int intel_me_read_mbp(me_bios_payload *mbp_data); /* MMIO base address for MEI interface */ static u32 *mei_base_address; - static void mei_dump(void *ptr, int dword, int offset, const char *type) { struct mei_csr *csr; @@ -292,7 +289,7 @@ static int mei_recv_msg(struct mkhi_header *mkhi, if (!mkhi_rsp.is_response || mkhi->group_id != mkhi_rsp.group_id || mkhi->command != mkhi_rsp.command) { - printk(BIOS_ERR, "ME: invalid response, group %u ?= %u," + printk(BIOS_ERR, "ME: invalid response, group %u ?= %u, " "command %u ?= %u, is_response %u\n", mkhi->group_id, mkhi_rsp.group_id, mkhi->command, mkhi_rsp.command, mkhi_rsp.is_response); @@ -568,6 +565,10 @@ static int intel_mei_setup(struct device *dev) return 0; } +#if CONFIG(CHROMEOS) +#include <vendorcode/google/chromeos/chromeos.h> +#endif + /* Read the Extend register hash of ME firmware */ static int intel_me_extend_valid(struct device *dev) { @@ -622,6 +623,8 @@ static void intel_me_hide(struct device *dev) pch_enable(dev); } +static int intel_me_read_mbp(me_bios_payload *mbp_data); + /* Check whether ME is present and do basic init */ static void intel_me_init(struct device *dev) { |