intel i945 gm45 x4x post-car: Use postcar_frame for MTRR setup

Adapt implementation from skylake to prepare for removal of
HIGH_MEMORY_SAVE and moving on to RELOCATABLE_RAMSTAGE.
With this change, CBMEM region is set early-on as WRBACK
with MTRRs and romstage ram stack is moved to CBMEM.

Change-Id: Idee5072fd499aa3815b0d78f54308c273e756fd1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15791
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

10 files changed, 204 insertions, 51 deletions

diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc
index 210d3566c7..d8a4fd9a83 100644
--- a/src/cpu/intel/car/cache_as_ram_ht.inc
+++ b/src/cpu/intel/car/cache_as_ram_ht.inc
@@ -337,10 +337,9 @@ before_romstage:
 	post_code(0x2f)
 	/* Call romstage.c main function. */
 	call	romstage_main
-
 	/* Save return value from romstage_main. It contains the stack to use
-	 * after cache-as-ram is torn down.
-	 */
+	 * after cache-as-ram is torn down. It also contains the information
+	 * for setting up MTRRs. */
 	movl	%eax, %esp
 
 	post_code(0x30)
@@ -378,27 +377,48 @@ before_romstage:
 
 	post_code(0x38)
 
-	/* Enable Write Back and Speculative Reads for low RAM. */
+	/* Clear all of the variable MTRRs. */
+	popl	%ebx
 	movl	$MTRR_PHYS_BASE(0), %ecx
-	movl	$(0x00000000 | MTRR_TYPE_WRBACK), %eax
-	xorl	%edx, %edx
-	wrmsr
-	movl	$MTRR_PHYS_MASK(0), %ecx
-	rdmsr
-	movl	$(~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax
-	wrmsr
+	clr	%eax
+	clr	%edx
+
+1:
+	testl	%ebx, %ebx
+	jz	1f
+	wrmsr			/* Write MTRR base. */
+	inc	%ecx
+	wrmsr			/* Write MTRR mask. */
+	inc	%ecx
+	dec	%ebx
+	jmp	1b
 
-#if CACHE_ROM_SIZE
-	/* Enable caching and Speculative Reads for Flash ROM device. */
-	movl	$MTRR_PHYS_BASE(1), %ecx
-	movl	$(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax
-	xorl	%edx, %edx
+1:
+	/* Get number of MTRRs. */
+	popl	%ebx
+	movl	$MTRR_PHYS_BASE(0), %ecx
+2:
+	testl	%ebx, %ebx
+	jz	2f
+
+	/* Low 32 bits of MTRR base. */
+	popl	%eax
+	/* Upper 32 bits of MTRR base. */
+	popl	%edx
+	/* Write MTRR base. */
 	wrmsr
-	movl	$MTRR_PHYS_MASK(1), %ecx
-	rdmsr
-	movl	$(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
+	inc	%ecx
+	/* Low 32 bits of MTRR mask. */
+	popl	%eax
+	/* Upper 32 bits of MTRR mask. */
+	popl	%edx
+	/* Write MTRR mask. */
 	wrmsr
-#endif
+	inc	%ecx
+
+	dec	%ebx
+	jmp	2b
+2:
 
 	post_code(0x39)
 
diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c
index 4f600342ec..14f841c08b 100644
--- a/src/cpu/intel/car/romstage.c
+++ b/src/cpu/intel/car/romstage.c
@@ -14,6 +14,7 @@
 #include <arch/cpu.h>
 #include <console/console.h>
 #include <cpu/intel/romstage.h>
+#include <cpu/x86/mtrr.h>
 #include <program_loading.h>
 
 #define DCACHE_RAM_ROMSTAGE_STACK_SIZE 0x2000
@@ -41,10 +42,7 @@ void * asmlinkage romstage_main(unsigned long bist)
 	}
 
 	/* Get the stack to use after cache-as-ram is torn down. */
-	if (IS_ENABLED(CONFIG_LATE_CBMEM_INIT))
-		romstage_stack_after_car = (void*)CONFIG_RAMTOP;
-	else
-		romstage_stack_after_car = setup_stack_and_mtrrs();
+	romstage_stack_after_car = setup_stack_and_mtrrs();
 
 	return romstage_stack_after_car;
 }
@@ -54,3 +52,26 @@ void asmlinkage romstage_after_car(void)
 	/* Load the ramstage. */
 	run_ramstage();
 }
+
+#if IS_ENABLED(CONFIG_LATE_CBMEM_INIT)
+/* setup_stack_and_mtrrs() determines the stack to use after
+ * cache-as-ram is torn down as well as the MTRR settings to use. */
+void *setup_stack_and_mtrrs(void)
+{
+	struct postcar_frame pcf;
+
+	postcar_frame_init_lowmem(&pcf);
+
+	/* Cache the ROM as WP just below 4GiB. */
+	postcar_frame_add_mtrr(&pcf, -CACHE_ROM_SIZE, CACHE_ROM_SIZE,
+		MTRR_TYPE_WRPROT);
+
+	/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
+	postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
+
+	/* Save the number of MTRRs to setup. Return the stack location
+	 * pointing to the number of MTRRs.
+	 */
+	return postcar_commit_mtrrs(&pcf);
+}
+#endif /* CONFIG_LATE_CBMEM_INIT */
diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc
index 1673242884..21f63ecae5 100644
--- a/src/cpu/intel/model_6ex/cache_as_ram.inc
+++ b/src/cpu/intel/model_6ex/cache_as_ram.inc
@@ -138,10 +138,9 @@ before_romstage:
 	post_code(0x29)
 	/* Call romstage.c main function. */
 	call	romstage_main
-
 	/* Save return value from romstage_main. It contains the stack to use
-	 * after cache-as-ram is torn down.
-	 */
+	 * after cache-as-ram is torn down. It also contains the information
+	 * for setting up MTRRs. */
 	movl	%eax, %esp
 
 	post_code(0x30)
@@ -179,27 +178,48 @@ before_romstage:
 
 	post_code(0x38)
 
-	/* Enable Write Back and Speculative Reads for low RAM. */
+	/* Clear all of the variable MTRRs. */
+	popl	%ebx
 	movl	$MTRR_PHYS_BASE(0), %ecx
-	movl	$(0x00000000 | MTRR_TYPE_WRBACK), %eax
-	xorl	%edx, %edx
+	clr	%eax
+	clr	%edx
+
+1:
+	testl	%ebx, %ebx
+	jz	1f
+	wrmsr			/* Write MTRR base. */
+	inc	%ecx
+	wrmsr			/* Write MTRR mask. */
+	inc	%ecx
+	dec	%ebx
+	jmp	1b
+
+1:
+	/* Get number of MTRRs. */
+	popl	%ebx
+	movl	$MTRR_PHYS_BASE(0), %ecx
+2:
+	testl	%ebx, %ebx
+	jz	2f
+
+	/* Low 32 bits of MTRR base. */
+	popl	%eax
+	/* Upper 32 bits of MTRR base. */
+	popl	%edx
+	/* Write MTRR base. */
 	wrmsr
-	movl	$MTRR_PHYS_MASK(0), %ecx
-	movl	$(~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax
-	movl	$CPU_PHYSMASK_HI, %edx
+	inc	%ecx
+	/* Low 32 bits of MTRR mask. */
+	popl	%eax
+	/* Upper 32 bits of MTRR mask. */
+	popl	%edx
+	/* Write MTRR mask. */
 	wrmsr
+	inc	%ecx
 
-#if CACHE_ROM_SIZE
-	/* Enable caching and Speculative Reads for Flash ROM device. */
-	movl	$MTRR_PHYS_BASE(1), %ecx
-	movl	$(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax
-	xorl	%edx, %edx
-	wrmsr
-	movl	$MTRR_PHYS_MASK(1), %ecx
-	movl	$(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
-	movl	$CPU_PHYSMASK_HI, %edx
-	wrmsr
-#endif
+	dec	%ebx
+	jmp	2b
+2:
 
 	post_code(0x39)
 
diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c
index bba53d1f68..821b87f52a 100644
--- a/src/mainboard/lenovo/t400/romstage.c
+++ b/src/mainboard/lenovo/t400/romstage.c
@@ -161,7 +161,6 @@ void mainboard_romstage_entry(unsigned long bist)
 	 * this is not a resume. In that case we just create the cbmem toc.
 	 */
 	if (s3resume && cbmem_initted) {
-		acpi_prepare_for_resume();
 
 		/* Magic for S3 resume */
 		pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_ACPI_S3_MAGIC);
diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c
index c1e193a973..8c97ae1554 100644
--- a/src/mainboard/lenovo/x200/romstage.c
+++ b/src/mainboard/lenovo/x200/romstage.c
@@ -162,7 +162,6 @@ void mainboard_romstage_entry(unsigned long bist)
 	 * this is not a resume. In that case we just create the cbmem toc.
 	 */
 	if (s3resume && cbmem_initted) {
-		acpi_prepare_for_resume();
 
 		/* Magic for S3 resume */
 		pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_ACPI_S3_MAGIC);
diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c
index 03cbf05106..e9a6a8182d 100644
--- a/src/mainboard/roda/rk9/romstage.c
+++ b/src/mainboard/roda/rk9/romstage.c
@@ -192,7 +192,6 @@ void mainboard_romstage_entry(unsigned long bist)
 	 * this is not a resume. In that case we just create the cbmem toc.
 	 */
 	if (s3resume && cbmem_initted) {
-		acpi_prepare_for_resume();
 
 		/* Magic for S3 resume */
 		pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_ACPI_S3_MAGIC);
diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c
index c22b491c66..780bed48b1 100644
--- a/src/northbridge/intel/gm45/ram_calc.c
+++ b/src/northbridge/intel/gm45/ram_calc.c
@@ -18,11 +18,14 @@
 #define __SIMPLE_DEVICE__
 
 #include <stdint.h>
+#include <arch/cpu.h>
 #include <arch/io.h>
 #include <device/pci_def.h>
 #include <console/console.h>
 #include <cpu/intel/romstage.h>
+#include <cpu/x86/mtrr.h>
 #include <cbmem.h>
+#include <program_loading.h>
 #include "gm45.h"
 
 /*
@@ -92,7 +95,36 @@ void *cbmem_top(void)
 	return (void *) top_of_ram;
 }
 
+#define ROMSTAGE_RAM_STACK_SIZE 0x5000
+
+/* setup_stack_and_mtrrs() determines the stack to use after
+ * cache-as-ram is torn down as well as the MTRR settings to use. */
 void *setup_stack_and_mtrrs(void)
 {
-	return (void*)CONFIG_RAMTOP;
+	struct postcar_frame pcf;
+	uintptr_t top_of_ram;
+
+	if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE))
+		die("Unable to initialize postcar frame.\n");
+
+	/* Cache the ROM as WP just below 4GiB. */
+	postcar_frame_add_mtrr(&pcf, -CACHE_ROM_SIZE, CACHE_ROM_SIZE,
+		MTRR_TYPE_WRPROT);
+
+	/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
+	postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
+
+	/* Cache two separate 4 MiB regions below the top of ram, this
+	 * satisfies MTRR alignment requirements. If you modify this to
+	 * cover TSEG, make sure UMA region is not set with WRBACK as it
+	 * causes hard-to-recover boot failures.
+	 */
+	top_of_ram = (uintptr_t)cbmem_top();
+	postcar_frame_add_mtrr(&pcf, top_of_ram - 4*MiB, 4*MiB, MTRR_TYPE_WRBACK);
+	postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 4*MiB, MTRR_TYPE_WRBACK);
+
+	/* Save the number of MTRRs to setup. Return the stack location
+	 * pointing to the number of MTRRs.
+	 */
+	return postcar_commit_mtrrs(&pcf);
 }
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index 16ae55f68a..8ebb422551 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -905,7 +905,6 @@ static void i945_prepare_resume(int s3resume)
 	 * this is not a resume. In that case we just create the cbmem toc.
 	 */
 	if (s3resume && cbmem_was_initted) {
-		acpi_prepare_for_resume();
 
 		/* Magic for S3 resume */
 		pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD,
diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c
index d962cc3daa..a8ef065fb2 100644
--- a/src/northbridge/intel/i945/ram_calc.c
+++ b/src/northbridge/intel/i945/ram_calc.c
@@ -17,10 +17,13 @@
 #define __SIMPLE_DEVICE__
 
 #include <arch/io.h>
+#include <arch/cpu.h>
 #include <cbmem.h>
 #include "i945.h"
 #include <console/console.h>
 #include <cpu/intel/romstage.h>
+#include <cpu/x86/mtrr.h>
+#include <program_loading.h>
 
 static uintptr_t smm_region_start(void)
 {
@@ -76,7 +79,36 @@ u32 decode_igd_memory_size(const u32 gms)
 	return ggc2uma[gms] << 10;
 }
 
+#define ROMSTAGE_RAM_STACK_SIZE 0x5000
+
+/* setup_stack_and_mtrrs() determines the stack to use after
+ * cache-as-ram is torn down as well as the MTRR settings to use. */
 void *setup_stack_and_mtrrs(void)
 {
-	return (void*)CONFIG_RAMTOP;
+	struct postcar_frame pcf;
+	uintptr_t top_of_ram;
+
+	if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE))
+		die("Unable to initialize postcar frame.\n");
+
+	/* Cache the ROM as WP just below 4GiB. */
+	postcar_frame_add_mtrr(&pcf, -CACHE_ROM_SIZE, CACHE_ROM_SIZE,
+		MTRR_TYPE_WRPROT);
+
+	/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
+	postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
+
+	/* Cache two separate 4 MiB regions below the top of ram, this
+	 * satisfies MTRR alignment requirements. If you modify this to
+	 * cover TSEG, make sure UMA region is not set with WRBACK as it
+	 * causes hard-to-recover boot failures.
+	 */
+	top_of_ram = (uintptr_t)cbmem_top();
+	postcar_frame_add_mtrr(&pcf, top_of_ram - 4*MiB, 4*MiB, MTRR_TYPE_WRBACK);
+	postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 4*MiB, MTRR_TYPE_WRBACK);
+
+	/* Save the number of MTRRs to setup. Return the stack location
+	 * pointing to the number of MTRRs.
+	 */
+	return postcar_commit_mtrrs(&pcf);
 }
diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/ram_calc.c
index 2a5d7e5752..410e3b623a 100644
--- a/src/northbridge/intel/x4x/ram_calc.c
+++ b/src/northbridge/intel/x4x/ram_calc.c
@@ -20,11 +20,14 @@
 #include <cbmem.h>
 #include <commonlib/helpers.h>
 #include <stdint.h>
+#include <arch/cpu.h>
 #include <arch/io.h>
 #include <device/pci_def.h>
 #include <console/console.h>
 #include <cpu/intel/romstage.h>
+#include <cpu/x86/mtrr.h>
 #include <northbridge/intel/x4x/x4x.h>
+#include <program_loading.h>
 
 /** Decodes used Graphics Mode Select (GMS) to kilobytes. */
 u32 decode_igd_memory_size(const u32 gms)
@@ -100,7 +103,36 @@ void *cbmem_top(void)
 	return (void *) top_of_ram;
 }
 
+#define ROMSTAGE_RAM_STACK_SIZE 0x5000
+
+/* setup_stack_and_mtrrs() determines the stack to use after
+ * cache-as-ram is torn down as well as the MTRR settings to use. */
 void *setup_stack_and_mtrrs(void)
 {
-	return (void*)CONFIG_RAMTOP;
+	struct postcar_frame pcf;
+	uintptr_t top_of_ram;
+
+	if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE))
+		die("Unable to initialize postcar frame.\n");
+
+	/* Cache the ROM as WP just below 4GiB. */
+	postcar_frame_add_mtrr(&pcf, -CACHE_ROM_SIZE, CACHE_ROM_SIZE,
+		MTRR_TYPE_WRPROT);
+
+	/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
+	postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
+
+	/* Cache two separate 4 MiB regions below the top of ram, this
+	 * satisfies MTRR alignment requirements. If you modify this to
+	 * cover TSEG, make sure UMA region is not set with WRBACK as it
+	 * causes hard-to-recover boot failures.
+	 */
+	top_of_ram = (uintptr_t)cbmem_top();
+	postcar_frame_add_mtrr(&pcf, top_of_ram - 4*MiB, 4*MiB, MTRR_TYPE_WRBACK);
+	postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 4*MiB, MTRR_TYPE_WRBACK);
+
+	/* Save the number of MTRRs to setup. Return the stack location
+	 * pointing to the number of MTRRs.
+	 */
+	return postcar_commit_mtrrs(&pcf);
 }