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authorMyles Watson <mylesgw@gmail.com>2010-09-02 22:02:53 +0000
committerMyles Watson <mylesgw@gmail.com>2010-09-02 22:02:53 +0000
commit8377c2d4bfabf69f42f7af86cea85bbd207473ab (patch)
tree9aee970f0a8b9a909c8c9c0cc564ee3914f6e464
parentdfe8d766fb5a561fb8b27007f5802c255f20167b (diff)
downloadcoreboot-8377c2d4bfabf69f42f7af86cea85bbd207473ab.tar.xz
Fix compilation for mtarvon. CAR initialization does early_mtrr_init,
jarell/debug.c isn't ready for gcc, and skip_romstage() doesn't compile. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5767 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
-rw-r--r--src/mainboard/intel/mtarvon/romstage.c9
1 files changed, 5 insertions, 4 deletions
diff --git a/src/mainboard/intel/mtarvon/romstage.c b/src/mainboard/intel/mtarvon/romstage.c
index 6d9d92f764..cdd0ed5573 100644
--- a/src/mainboard/intel/mtarvon/romstage.c
+++ b/src/mainboard/intel/mtarvon/romstage.c
@@ -33,7 +33,6 @@
#include "southbridge/intel/i3100/i3100_early_lpc.c"
#include "northbridge/intel/i3100/raminit.h"
#include "superio/intel/i3100/i3100.h"
-#include "cpu/x86/lapic/boot_cpu.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "superio/intel/i3100/i3100_early_serial.c"
#include "northbridge/intel/i3100/memory_initialized.c"
@@ -52,10 +51,11 @@ static inline int spd_read_byte(u16 device, u8 address)
#include "northbridge/intel/i3100/raminit.c"
#include "lib/generic_sdram.c"
-#include "../jarrell/debug.c"
+#if 0 /* skip_romstage doesn't compile with gcc */
#include "arch/i386/lib/stages.c"
+#endif
-static void main(unsigned long bist)
+void main(unsigned long bist)
{
msr_t msr;
u16 perf;
@@ -72,11 +72,12 @@ static void main(unsigned long bist)
};
if (bist == 0) {
+#if 0 /* skip_romstage doesn't compile with gcc */
/* Skip this if there was a built in self test failure */
- early_mtrr_init();
if (memory_initialized()) {
skip_romstage();
}
+#endif
}
/* Set up the console */
i3100_enable_superio();