diff options
| author | Michael Niewöhner <foss@mniewoehner.de> | 2020-12-19 22:22:32 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2020-12-22 20:34:27 +0000 |
| commit | 8ba96b91dc1559c5a88bad5b4384885d3b384f11 (patch) | |
| tree | 029e28c6f65fe0550cc0e21a55e1fae57a11397f | |
| parent | e653942453f6537606417cefc1d16d8962166b10 (diff) | |
| download | coreboot-8ba96b91dc1559c5a88bad5b4384885d3b384f11.tar.xz | |
soc/intel/apl/graphics: add missing left-shift
According to doc# IHD-OS-BXT-Vol 2b-05.17 the cycle delay is in the bit
range 8:4 of register PP_CONTROL. The current code writes the value to
bits 4:0, though. Correct that by shifting the value left by 4 bits.
Change-Id: If407932c847da39b19e307368c9e52ba1c93bccd
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
| -rw-r--r-- | src/soc/intel/apollolake/graphics.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/intel/apollolake/graphics.c b/src/soc/intel/apollolake/graphics.c index 24d47721ab..be13b5b825 100644 --- a/src/soc/intel/apollolake/graphics.c +++ b/src/soc/intel/apollolake/graphics.c @@ -17,7 +17,8 @@ static void graphics_configure_panelpower( const unsigned int offset = panel_idx * 0x100; uint32_t reg32; - reg32 = ((DIV_ROUND_UP(pp->cycle_delay_ms, 100) + 1) & 0x1f) | PANEL_POWER_RESET; + reg32 = (DIV_ROUND_UP(pp->cycle_delay_ms, 100) + 1) << 4 & 0x1f0; + reg32 |= PANEL_POWER_RESET; write32(mmio + PCH_PP_CONTROL + offset, reg32); reg32 = pp->up_delay_ms * 10 << 16; |