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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-25 06:56:04 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-26 11:42:52 +0000 |
| commit | 8d82109c08163fa82263b35e9aa0a270a795a5f8 (patch) | |
| tree | d603e3e4919fbb16abec3cc6f44542c1b5a35e4c | |
| parent | c61d415701a42c04bf5b24cfc4f07a5b4ee75d81 (diff) | |
| download | coreboot-8d82109c08163fa82263b35e9aa0a270a795a5f8.tar.xz | |
nb/intel/sandybridge: Fix mrc.bin path
The mrc.bin uses a lot of stack. The BSP stack size is kept
the same for both romstage bootpaths, mrc.bin and native,
in order for the CAR symbol/setups to be compatible.
Change-Id: Ic422980ca1a0549b6937e30a433ce52e0d7a595c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37185
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/northbridge/intel/sandybridge/Kconfig | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 0502b50014..7a27d098c5 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -74,7 +74,10 @@ config DCACHE_RAM_BASE config DCACHE_BSP_STACK_SIZE hex - default 0x2800 + default 0x10000 + help + The amount of BSP stack anticipated in bootblock and + other stages. if USE_NATIVE_RAMINIT |