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authorMarc Jones <marcj303@gmail.com>2017-07-12 11:05:38 -0600
committerMartin Roth <martinroth@google.com>2017-08-04 14:22:18 +0000
commit9156cac2ef9e7d07de92b4e1430518a9918cf52d (patch)
tree96690057c8f103faa7dfb7ef3ec449b17baf6c54
parentdfdea2aa40ab5bebea580601f6cef70bec25e177 (diff)
downloadcoreboot-9156cac2ef9e7d07de92b4e1430518a9918cf52d.tar.xz
soc/amd/stoneyridge: Use generic gpio library
Use the genric GPIO library. Add the required functions. Also, update the Kahlee mainboard dependency to match. Change-Id: I2ea562b052401efff3101f736788ca77d21e6de6 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20543 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/mainboard/google/kahlee/chromeos.c2
-rw-r--r--src/soc/amd/stoneyridge/Kconfig1
-rw-r--r--src/soc/amd/stoneyridge/gpio.c52
-rw-r--r--src/soc/amd/stoneyridge/include/soc/gpio.h7
4 files changed, 58 insertions, 4 deletions
diff --git a/src/mainboard/google/kahlee/chromeos.c b/src/mainboard/google/kahlee/chromeos.c
index 4112db5677..156614bbb8 100644
--- a/src/mainboard/google/kahlee/chromeos.c
+++ b/src/mainboard/google/kahlee/chromeos.c
@@ -18,7 +18,7 @@
#include <vendorcode/google/chromeos/chromeos.h>
#include <boot/coreboot_tables.h>
#include <console/console.h>
-#include <soc/gpio.h>
+#include <gpio.h>
/* SPI Write protect */
#define CROS_WP_GPIO GPIO_122
diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
index f1f2c12e35..0425bebd0f 100644
--- a/src/soc/amd/stoneyridge/Kconfig
+++ b/src/soc/amd/stoneyridge/Kconfig
@@ -31,6 +31,7 @@ config CPU_SPECIFIC_OPTIONS
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
+ select GENERIC_GPIO_LIB
select IOAPIC
select HAVE_USBDEBUG_OPTIONS
select HAVE_HARD_RESET
diff --git a/src/soc/amd/stoneyridge/gpio.c b/src/soc/amd/stoneyridge/gpio.c
index d49637a09c..7e19d996ff 100644
--- a/src/soc/amd/stoneyridge/gpio.c
+++ b/src/soc/amd/stoneyridge/gpio.c
@@ -16,8 +16,11 @@
*/
#include <arch/io.h>
+#include <gpio.h>
#include <soc/gpio.h>
+/* The following functions must be implemented by SoC/board code. */
+
int gpio_get(gpio_t gpio_num)
{
uint32_t reg;
@@ -26,3 +29,52 @@ int gpio_get(gpio_t gpio_num)
return !!(reg & GPIO_PIN_STS);
}
+
+
+void gpio_set(gpio_t gpio_num, int value)
+{
+ uint32_t reg;
+
+ reg = read32((void *)(uintptr_t)gpio_num);
+ reg &= ~GPIO_OUTPUT_MASK;
+ reg |= !!value << GPIO_OUTPUT_SHIFT;
+ write32((void *)(uintptr_t)gpio_num, reg);
+}
+
+void gpio_input_pulldown(gpio_t gpio_num)
+{
+ uint32_t reg;
+
+ reg = read32((void *)(uintptr_t)gpio_num);
+ reg &= ~GPIO_PULLUP_ENABLE;
+ reg |= GPIO_PULLDOWN_ENABLE;
+ write32((void *)(uintptr_t)gpio_num, reg);
+}
+
+void gpio_input_pullup(gpio_t gpio_num)
+{
+ uint32_t reg;
+
+ reg = read32((void *)(uintptr_t)gpio_num);
+ reg &= ~GPIO_PULLDOWN_ENABLE;
+ reg |= GPIO_PULLUP_ENABLE;
+ write32((void *)(uintptr_t)gpio_num, reg);
+}
+
+void gpio_input(gpio_t gpio_num)
+{
+ uint32_t reg;
+
+ reg = read32((void *)(uintptr_t)gpio_num);
+ reg &= ~GPIO_OUTPUT_ENABLE;
+ write32((void *)(uintptr_t)gpio_num, reg);
+}
+
+void gpio_output(gpio_t gpio_num, int value)
+{
+ uint32_t reg;
+
+ reg = read32((void *)(uintptr_t)gpio_num);
+ reg |= GPIO_OUTPUT_ENABLE;
+ write32((void *)(uintptr_t)gpio_num, reg);
+}
diff --git a/src/soc/amd/stoneyridge/include/soc/gpio.h b/src/soc/amd/stoneyridge/include/soc/gpio.h
index f873e52152..c43dd2767a 100644
--- a/src/soc/amd/stoneyridge/include/soc/gpio.h
+++ b/src/soc/amd/stoneyridge/include/soc/gpio.h
@@ -22,7 +22,10 @@
#define CROS_GPIO_DEVICE_NAME "AmdKern"
#define GPIO_PIN_STS (1 << 16)
-#define GPIO_OUTPUT_VALUE (1 << 22)
+#define GPIO_PULLUP_ENABLE (1 << 20)
+#define GPIO_PULLDOWN_ENABLE (1 << 21)
+#define GPIO_OUTPUT_SHIFT 22
+#define GPIO_OUTPUT_MASK (1 << GPIO_OUTPUT_SHIFT)
#define GPIO_OUTPUT_ENABLE (1 << 23)
/* GPIO_0 - GPIO_62 */
@@ -126,6 +129,4 @@
typedef uint32_t gpio_t;
-int gpio_get(gpio_t gpio_num);
-
#endif /* _STONEYRIDGE_GPIO_H_ */