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authorMarshall Dawson <marshalldawson3rd@gmail.com>2019-06-30 13:07:26 -0500
committerMartin Roth <martinroth@google.com>2019-10-20 16:43:05 +0000
commit9269be630b94653b599edd4b42ca2a8b992c857f (patch)
tree9efe6533a9fa90e13bb5b290b96304cef9b169c9
parentc0b8d0d5b5bd3f43e607ee317447d0a27fb5d474 (diff)
downloadcoreboot-9269be630b94653b599edd4b42ca2a8b992c857f.tar.xz
soc/amd/picasso: Update iomap
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Ieedc2062948a0d1563f82e4d0b1ca9c5bc3291a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33991 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/soc/amd/picasso/include/soc/iomap.h34
1 files changed, 21 insertions, 13 deletions
diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h
index 344b8865ed..5037a1c2c5 100644
--- a/src/soc/amd/picasso/include/soc/iomap.h
+++ b/src/soc/amd/picasso/include/soc/iomap.h
@@ -22,6 +22,11 @@
#define SPI_BASE_ADDRESS 0xfec10000
#define ESPI_BASE_ADDRESS 0xfec20000
+#if CONFIG(HPET_ADDRESS_OVERRIDE)
+#error HPET address override is not allowed and must be fixed at 0xfed00000
+#endif
+#define HPET_BASE_ADDRESS 0xfed00000
+
/*
* AcpiMmio blocks are at fixed offsets from FED8_0000h and enabled in PMx04[1].
* All ranges not specified as supported below may, or may not, be listed in
@@ -44,27 +49,30 @@
#define ALINK_AHB_ADDRESS 0xfedc0000
-/* I2C fixed address */
+/* Reserved 0xfecd1000-0xfedc3fff */
+
#define APU_I2C2_BASE 0xfedc4000
#define APU_I2C3_BASE 0xfedc5000
#define APU_I2C4_BASE 0xfedc6000
-#define APU_I2C_MIN_BUS 2
-#define APU_I2C_MAX_BUS 4
-#define APU_I2C_BLOCK_SIZE 0x1000
-#define I2C_BASE_ADDRESS APU_I2C2_BASE
-#define I2C_DEVICE_SIZE 0x00001000
-#define I2C_DEVICE_COUNT 3
-
-
-#if CONFIG(HPET_ADDRESS_OVERRIDE)
-#error HPET address override is not allowed and must be fixed at 0xfed00000
-#endif
-#define HPET_BASE_ADDRESS 0xfed00000
+#define APU_I2C_MIN_BUS 2
+#define APU_I2C_MAX_BUS 4
+#define APU_I2C_BLOCK_SIZE 0x1000
+#define I2C_BASE_ADDRESS APU_I2C2_BASE
+#define I2C_DEVICE_SIZE 0x00001000
+#define I2C_DEVICE_COUNT 3
+#define APU_DMAC0_BASE 0xfedc7000
+#define APU_DMAC1_BASE 0xfedc8000
#define APU_UART0_BASE 0xfedc9000
#define APU_UART1_BASE 0xfedca000
+/* Reserved 0xfedcb000 */
+#define APU_DMAC2_BASE 0xfedcc000
+#define APU_DMAC3_BASE 0xfedcd000
#define APU_UART2_BASE 0xfedce000
#define APU_UART3_BASE 0xfedcf000
+/* Reserved 0xfedd0000-0xfedd4fff */
+#define APU_EMMC_BASE 0xfedd5000
+#define APU_EMMC_CONFIG_BASE 0xfedd5800
#define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1)