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authorKeith Hui <buurin@gmail.com>2020-01-11 13:49:59 -0500
committerPatrick Georgi <pgeorgi@google.com>2020-01-14 18:19:14 +0000
commit9b4b33ac37494d0d7ae510478981c8a5b77af1d0 (patch)
treed3998f198ff3d6f3b5216201c015bbb249a330b2
parentf555a58abc487270d4ba42527b1b43850bd718c0 (diff)
downloadcoreboot-9b4b33ac37494d0d7ae510478981c8a5b77af1d0.tar.xz
sb/intel/i82371eb: Add PIIX4 definitions
These new definitions will be used by two other changes. Change-Id: I242244c444f36af188c871dce037a7a9250206cd Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38367 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/southbridge/intel/i82371eb/i82371eb.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h
index 2b530102e3..a566af7767 100644
--- a/src/southbridge/intel/i82371eb/i82371eb.h
+++ b/src/southbridge/intel/i82371eb/i82371eb.h
@@ -40,6 +40,11 @@ int smbus_read_byte(u8 device, u8 address);
#define XBCS 0x4e /* X-Bus chip select register */
#define GENCFG 0xb0 /* General configuration register */
+#define GPO2223 (1<<28) /* GPO22/23 */
+#define RTCCFG 0xcb /* Real time clock configuration register */
+#define RTC_POS_DECODE (1<<5)
+#define UPPER_RAM_EN (1<<2)
+#define RTC_ENABLE (1<<0)
/* IDE */
#define IDETIM_PRI 0x40 /* IDE timing register, primary channel */