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| author | Matt Ziegelbaum <ziegs@google.com> | 2020-11-17 17:20:04 -0500 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-11-18 18:48:29 +0000 |
| commit | a04072c91743eed03574c6b3e42bdf450b136009 (patch) | |
| tree | 512b0fdbccc48b2cb726b40f828ca6bae5f63662 | |
| parent | 552133e161c5b704cbe9e1db3c673ceb64089498 (diff) | |
| download | coreboot-a04072c91743eed03574c6b3e42bdf450b136009.tar.xz | |
mb/google/hatch/var/ambassador: configure FSP option PcieRpSlotImplemented
Ambassador is similar to puff. This change matches the
PcieRpSlotImplemented configuration with Puff's, originally made for
Puff in https://review.coreboot.org/c/coreboot/+/39986.
Signed-off-by: Matt Ziegelbaum <ziegs@google.com>
Change-Id: I5b6246f58c10e03a0d02278ad3621ded39bb6d6e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
| -rw-r--r-- | src/mainboard/google/hatch/variants/ambassador/overridetree.cb | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/mainboard/google/hatch/variants/ambassador/overridetree.cb b/src/mainboard/google/hatch/variants/ambassador/overridetree.cb index 7b4615320f..7cc920d7ee 100644 --- a/src/mainboard/google/hatch/variants/ambassador/overridetree.cb +++ b/src/mainboard/google/hatch/variants/ambassador/overridetree.cb @@ -402,8 +402,11 @@ chip soc/intel/cannonlake register "device_index" = "0" device pci 00.0 on end end + register "PcieRpSlotImplemented[6]" = "1" end # RTL8111H Ethernet NIC - device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe) + device pci 1d.2 on # PCI Express Port 11 (X2 NVMe) + register "PcieRpSlotImplemented[10]" = "1" + end device pci 1e.3 off end # GSPI #1 end |