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authorAaron Durbin <adurbin@chromium.org>2017-08-14 12:08:43 -0600
committerAaron Durbin <adurbin@chromium.org>2017-08-15 19:01:13 +0000
commita045fb9de8602ca44d312c997ee607ab86c41ba4 (patch)
treef145a648bc298fcad28d58440a9d3beeebf60ad3
parent40b2ae3ff84b52bbaeec6e4b7ee7b14248f54450 (diff)
downloadcoreboot-a045fb9de8602ca44d312c997ee607ab86c41ba4.tar.xz
soc/intel/{cannonlake,skylake}: fix PCH_P2SB_EPMASK macro
The PCH_P2SB_EPMASK macro takes a parameter. Ensure parenthesis are put around the parameter expansion. Change-Id: I978e9397036ea3630434982fe4ecd698877fe0d6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
-rw-r--r--src/soc/intel/cannonlake/include/soc/p2sb.h2
-rw-r--r--src/soc/intel/skylake/include/soc/p2sb.h2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/cannonlake/include/soc/p2sb.h b/src/soc/intel/cannonlake/include/soc/p2sb.h
index 1f209ed862..8b2e437f87 100644
--- a/src/soc/intel/cannonlake/include/soc/p2sb.h
+++ b/src/soc/intel/cannonlake/include/soc/p2sb.h
@@ -20,7 +20,7 @@
#define HPTC_ADDR_ENABLE_BIT (1 << 7)
#define PCH_P2SB_EPMASK0 0x220
-#define PCH_P2SB_EPMASK(mask_number) (PCH_P2SB_EPMASK0 + (mask_number * 4))
+#define PCH_P2SB_EPMASK(mask_number) (PCH_P2SB_EPMASK0 + ((mask_number) * 4))
#define PCH_P2SB_E0 0xE0
diff --git a/src/soc/intel/skylake/include/soc/p2sb.h b/src/soc/intel/skylake/include/soc/p2sb.h
index 36bb62d675..d846dfc8f5 100644
--- a/src/soc/intel/skylake/include/soc/p2sb.h
+++ b/src/soc/intel/skylake/include/soc/p2sb.h
@@ -20,7 +20,7 @@
#define HPTC_ADDR_ENABLE_BIT (1 << 7)
#define PCH_P2SB_EPMASK0 0xB0
-#define PCH_P2SB_EPMASK(mask_number) (PCH_P2SB_EPMASK0 + (mask_number * 4))
+#define PCH_P2SB_EPMASK(mask_number) (PCH_P2SB_EPMASK0 + ((mask_number) * 4))
#define PCH_P2SB_E0 0xE0
#define PCH_PWRM_ACPI_TMR_CTL 0xFC