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authorBill XIE <persmule@hardenedlinux.org>2020-01-24 23:20:57 +0800
committerPatrick Georgi <pgeorgi@google.com>2020-01-27 07:45:06 +0000
commita3a1a1c39bd530fe8bf64ef77fc4b34bbfe8b253 (patch)
tree82ce450aec143a12ce15c2f7564dbc483d523175
parentdd80b5c7a15ed5d4dd3ca88d4e0a4dbe5221249c (diff)
downloadcoreboot-a3a1a1c39bd530fe8bf64ef77fc4b34bbfe8b253.tar.xz
mb/gigabyte/ga-b75m-d3h: add ACPI definitions for legacy PCI slots
All variants of ga-b75m-d3h lack ACPI definitions for legacy PCI slots, which causes IRQ issue if it gets legacy PCI card installed. The missing definitions (mainly Interrupt Routing Table) are added to fix that. NOTE: The added definitions are actually for ga-b75-d3v, but since they form superset of definitions needed by ga-b75m-d3{h,v}, they can be applied to all three existing variants with suitable preprocessor instructions. Change-Id: Id79c759a5fadb38c2873edc07293cbb14401ac9a Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
-rw-r--r--src/mainboard/gigabyte/ga-b75m-d3h/acpi/pci.asl53
-rw-r--r--src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl1
2 files changed, 54 insertions, 0 deletions
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/pci.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/pci.asl
new file mode 100644
index 0000000000..e98c0a2286
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/pci.asl
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2020 Bill Xie <persmule@hardenedlinux.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+// Intel PCI to PCI bridge 0:1e.0
+
+Device (PCIB)
+{
+ Name (_ADR, 0x001E0000) // _ADR: Address
+ Name (_PRW, Package(){ 13, 4 }) // Power Resources for Wake
+
+ Method (_PRT) // _PRT: PCI Interrupt Routing Table
+ {
+ If (PICM) {
+ Return (Package() {
+ Package() { 0x0001ffff, 0, 0, 0x13 },
+ Package() { 0x0001ffff, 1, 0, 0x12 },
+ Package() { 0x0001ffff, 2, 0, 0x10 },
+ Package() { 0x0001ffff, 3, 0, 0x14 },
+#if CONFIG(BOARD_GIGABYTE_GA_B75_D3V)
+ Package() { 0x0002ffff, 0, 0, 0x12 },
+ Package() { 0x0002ffff, 1, 0, 0x10 },
+ Package() { 0x0002ffff, 2, 0, 0x14 },
+ Package() { 0x0002ffff, 3, 0, 0x13 },
+#endif
+ })
+ }
+ Return (Package() {
+ Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+ Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
+ Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
+ Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKE, 0 },
+#if CONFIG(BOARD_GIGABYTE_GA_B75_D3V)
+ Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
+ Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKA, 0 },
+ Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKE, 0 },
+ Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
+#endif
+ })
+ }
+}
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl b/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl
index 47b2725cd7..91ed5511d4 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl
@@ -37,6 +37,7 @@ DefinitionBlock(
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+ #include "acpi/pci.asl"
}
}
}