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author | Matt DeVillier <matt.devillier@gmail.com> | 2017-04-17 18:26:58 -0500 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2017-05-31 19:10:10 +0200 |
commit | a672d155a217b70a5bb6505a36ba65c3a8f90137 (patch) | |
tree | bbb53d0cd6c820e69d95e9953d910b907b73540d | |
parent | 8b96fd2e5affcf4420268d53fa58826685ccbeed (diff) | |
download | coreboot-a672d155a217b70a5bb6505a36ba65c3a8f90137.tar.xz |
sb/lynxpoint: add missing USB port defs
Add device/address stubs for XHCI USB ports 7, 10-13.
Stub data will be supplemented by board-specific info
added in subsequent commits.
Change-Id: I7d2f93351435cccd62e8fe4d95ad3467aa09de69
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19965
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r-- | src/southbridge/intel/lynxpoint/acpi/usb.asl | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/src/southbridge/intel/lynxpoint/acpi/usb.asl b/src/southbridge/intel/lynxpoint/acpi/usb.asl index 85e439036f..ee883031ed 100644 --- a/src/southbridge/intel/lynxpoint/acpi/usb.asl +++ b/src/southbridge/intel/lynxpoint/acpi/usb.asl @@ -49,7 +49,6 @@ Device (EHCI) { Name (_ADR, 0x00000000) - // How many are there? Device (PRT1) { Name (_ADR, 1) } // USB Port 0 Device (PRT2) { Name (_ADR, 2) } // USB Port 1 Device (PRT3) { Name (_ADR, 3) } // USB Port 2 @@ -409,12 +408,16 @@ Device (XHCI) Return (PCKG) } - // How many are there? Device (PRT1) { Name (_ADR, 1) } // USB Port 0 Device (PRT2) { Name (_ADR, 2) } // USB Port 1 Device (PRT3) { Name (_ADR, 3) } // USB Port 2 Device (PRT4) { Name (_ADR, 4) } // USB Port 3 Device (PRT5) { Name (_ADR, 5) } // USB Port 4 Device (PRT6) { Name (_ADR, 6) } // USB Port 5 + Device (PRT7) { Name (_ADR, 7) } // USB Port 6 + Device (SSP1) { Name (_ADR, 10) } // USB Port 10 + Device (SSP2) { Name (_ADR, 11) } // USB Port 11 + Device (SSP3) { Name (_ADR, 12) } // USB Port 12 + Device (SSP4) { Name (_ADR, 13) } // USB Port 13 } } |