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author | Yidi Lin <yidi.lin@mediatek.com> | 2020-11-20 14:03:20 +0800 |
---|---|---|
committer | Hung-Te Lin <hungte@chromium.org> | 2020-11-21 13:36:23 +0000 |
commit | aad4651e3eab260c94058536d373b2ff22b40d92 (patch) | |
tree | c2ed69daf358d06b97360eabd74371b577969a9a | |
parent | 1e37c9ca465a14d55adeacb332354771543437b5 (diff) | |
download | coreboot-aad4651e3eab260c94058536d373b2ff22b40d92.tar.xz |
mb/google/asurada: Get RAM code from ADC 3
On Chromebooks the RAM code is implemented by the resistor straps
that we can read and decode from ADC. For Asurada the RAM code can be
read from ADC channel 3.
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: Iaadabea1b6aa91c48b137f7c6784ab7ee0adc473
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
-rw-r--r-- | src/mainboard/google/asurada/boardid.c | 57 |
1 files changed, 56 insertions, 1 deletions
diff --git a/src/mainboard/google/asurada/boardid.c b/src/mainboard/google/asurada/boardid.c index 2c8efcddd8..cb91812bbf 100644 --- a/src/mainboard/google/asurada/boardid.c +++ b/src/mainboard/google/asurada/boardid.c @@ -1,9 +1,59 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <assert.h> #include <boardid.h> +#include <console/console.h> +#include <soc/auxadc.h> /* board_id is provided by ec/google/chromeec/ec_boardid.c */ +#define ADC_LEVELS 15 + +enum { + RAM_ID_CHANNEL = 3, +}; + +static const unsigned int ram_voltages[ADC_LEVELS] = { + /* ID : Voltage (unit: uV) */ + [0] = 74300, + [1] = 211700, + [2] = 318800, + [3] = 428600, + [4] = 541700, + [5] = 665800, + [6] = 781400, + [7] = 900000, + [8] = 1023100, + [9] = 1137000, + [10] = 1240000, + [11] = 1342600, + [12] = 1457500, + [13] = 1575600, + [14] = 1683600, +}; + +static const unsigned int *adc_voltages[] = { + [RAM_ID_CHANNEL] = ram_voltages, +}; + +static uint32_t get_adc_index(unsigned int channel) +{ + unsigned int value = auxadc_get_voltage_uv(channel); + + assert(channel < ARRAY_SIZE(adc_voltages)); + const unsigned int *voltages = adc_voltages[channel]; + assert(voltages); + + /* Find the closest voltage */ + uint32_t id; + for (id = 0; id < ADC_LEVELS - 1; id++) + if (value < (voltages[id] + voltages[id + 1]) / 2) + break; + + printk(BIOS_DEBUG, "ADC[%u]: Raw value=%u ID=%u\n", channel, value, id); + return id; +} + uint32_t sku_id(void) { return 0; @@ -11,5 +61,10 @@ uint32_t sku_id(void) uint32_t ram_code(void) { - return 0; + static uint32_t cached_ram_code = BOARD_ID_INIT; + + if (cached_ram_code == BOARD_ID_INIT) + cached_ram_code = get_adc_index(RAM_ID_CHANNEL); + + return cached_ram_code; } |