baytrail: Clean up NVS region

There is a lot of NVS allocated to things that are not really
used.  Most of these are removed and some are moved around.
Thermals are expected to be handled with DPTF so I've removed
that bit of code but have not yet cleaned up the thermal zone.

I left in the SIO BARs since I think we will need those still
even though they may need work still.

BUG=chrome-os-partner:23505
BRANCH=rambi
TEST=build and boot on rambi

Change-Id: Id16ee67e6b3709a303c001afd72947147f938127
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175626
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4936
Tested-by: build bot (Jenkins)

3 files changed, 43 insertions, 317 deletions

diff --git a/src/mainboard/google/rambi/acpi_tables.c b/src/mainboard/google/rambi/acpi_tables.c
index 0b9622807a..f61db1d65f 100644
--- a/src/mainboard/google/rambi/acpi_tables.c
+++ b/src/mainboard/google/rambi/acpi_tables.c
@@ -30,45 +30,16 @@
 #include <device/pci_ids.h>
 #include <cpu/cpu.h>
 #include <cpu/x86/msr.h>
+#include <ec/google/chromeec/ec.h>
 #include <vendorcode/google/chromeos/gnvs.h>
 #include <baytrail/acpi.h>
 #include <baytrail/nvs.h>
+#include <baytrail/iomap.h>
 
 extern const unsigned char AmlCode[];
 
-#include "thermal.h"
-
-static void acpi_update_thermal_table(global_nvs_t *gnvs)
-{
-	gnvs->f4of = FAN4_THRESHOLD_OFF;
-	gnvs->f4on = FAN4_THRESHOLD_ON;
-	gnvs->f4pw = FAN4_PWM;
-
-	gnvs->f3of = FAN3_THRESHOLD_OFF;
-	gnvs->f3on = FAN3_THRESHOLD_ON;
-	gnvs->f3pw = FAN3_PWM;
-
-	gnvs->f2of = FAN2_THRESHOLD_OFF;
-	gnvs->f2on = FAN2_THRESHOLD_ON;
-	gnvs->f2pw = FAN2_PWM;
-
-	gnvs->f1of = FAN1_THRESHOLD_OFF;
-	gnvs->f1on = FAN1_THRESHOLD_ON;
-	gnvs->f1pw = FAN1_PWM;
-
-	gnvs->f0of = FAN0_THRESHOLD_OFF;
-	gnvs->f0on = FAN0_THRESHOLD_ON;
-	gnvs->f0pw = FAN0_PWM;
-
-	gnvs->tcrt = CRITICAL_TEMPERATURE;
-	gnvs->tpsv = PASSIVE_TEMPERATURE;
-	gnvs->tmax = MAX_TEMPERATURE;
-}
-
 static void acpi_create_gnvs(global_nvs_t *gnvs)
 {
-	gnvs->apic = 1;
-	gnvs->mpen = 1; /* Enable Multi Processing */
 	gnvs->pcnt = dev_count_cpu();
 
 	/* Enable USB ports in S3 */
@@ -82,28 +53,20 @@ static void acpi_create_gnvs(global_nvs_t *gnvs)
 	/* CBMEM TOC */
 	gnvs->cmem = 0;
 
+	/* Top of Low Memory (start of resource allocation) */
+	gnvs->tolm = nc_read_top_of_low_memory();
+
 	/* TPM Present */
 	gnvs->tpmp = 1;
 
-	/* IGD Displays */
-	gnvs->ndid = 3;
-	gnvs->did[0] = 0x80000100;
-	gnvs->did[1] = 0x80000240;
-	gnvs->did[2] = 0x80000410;
-	gnvs->did[3] = 0x80000410;
-	gnvs->did[4] = 0x00000005;
-
 #if CONFIG_CHROMEOS
-	// TODO(reinauer) this could move elsewhere?
 	chromeos_init_vboot(&(gnvs->chromeos));
-	/* Emerald Lake has no EC (?) */
-	gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
+	gnvs->chromeos.vbt2 = google_ec_running_ro() ?
+		ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
 #endif
 
 	/* Update the mem console pointer. */
 	gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE);
-
-	acpi_update_thermal_table(gnvs);
 }
 
 unsigned long acpi_fill_madt(unsigned long current)
diff --git a/src/soc/intel/baytrail/acpi/globalnvs.asl b/src/soc/intel/baytrail/acpi/globalnvs.asl
index 5b000930d1..37a234c485 100644
--- a/src/soc/intel/baytrail/acpi/globalnvs.asl
+++ b/src/soc/intel/baytrail/acpi/globalnvs.asl
@@ -22,7 +22,6 @@
 /* Global Variables */
 
 Name(\PICM, 0)		// IOAPIC/8259
-Name(\DSEN, 1)		// Display Output Switching Enable
 
 /* Global ACPI memory region. This region is used for passing information
  * between coreboot (aka "the system bios"), ACPI, and the SMI handler.
@@ -49,69 +48,23 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	P80D,	32,	// 0x0b - Debug port (IO 0x80) value
 	LIDS,	 8,	// 0x0f - LID state (open = 1)
 	PWRS,	 8,	// 0x10 - Power State (AC = 1)
-	/* Thermal policy */
-	Offset (0x11),
-	TLVL,    8,	// 0x11 - Throttle Level Limit
-	FLVL,	 8,	// 0x12 - Current FAN Level
-	TCRT,    8,	// 0x13 - Critical Threshold
-	TPSV,	 8,	// 0x14 - Passive Threshold
-	TMAX,	 8,	// 0x15 - CPU Tj_max
-	F0OF,	 8,	// 0x16 - FAN 0 OFF Threshold
-	F0ON,	 8,	// 0x17 - FAN 0 ON Threshold
-	F0PW,	 8,	// 0x18 - FAN 0 PWM value
-	F1OF,	 8,	// 0x19 - FAN 1 OFF Threshold
-	F1ON,	 8,	// 0x1a - FAN 1 ON Threshold
-	F1PW,	 8,	// 0x1b - FAN 1 PWM value
-	F2OF,	 8,	// 0x1c - FAN 2 OFF Threshold
-	F2ON,	 8,	// 0x1d - FAN 2 ON Threshold
-	F2PW,	 8,	// 0x1e - FAN 2 PWM value
-	F3OF,	 8,	// 0x1f - FAN 3 OFF Threshold
-	F3ON,	 8,	// 0x20 - FAN 3 ON Threshold
-	F3PW,	 8,	// 0x21 - FAN 3 PWM value
-	F4OF,	 8,	// 0x22 - FAN 4 OFF Threshold
-	F4ON,	 8,	// 0x23 - FAN 4 ON Threshold
-	F4PW,	 8,	// 0x24 - FAN 4 PWM value
-	TMPS,    8,	// 0x25 - Temperature Sensor ID
-	/* Processor Identification */
-	Offset (0x28),
-	APIC,	 8,	// 0x28 - APIC Enabled by coreboot
-	MPEN,	 8,	// 0x29 - Multi Processor Enable
-	PCP0,	 8,	// 0x2a - PDC CPU/CORE 0
-	PCP1,	 8,	// 0x2b - PDC CPU/CORE 1
-	PPCM,	 8,	// 0x2c - Max. PPC state
-	PCNT,	 8,	// 0x2d - Processor count
-	/* Super I/O & CMOS config */
-	Offset (0x32),
-	NATP,	 8,	// 0x32 -
-	S5U0,	 8,	// 0x33 - Enable USB0 in S5
-	S5U1,	 8,	// 0x34 - Enable USB1 in S5
-	S3U0,	 8,	// 0x35 - Enable USB0 in S3
-	S3U1,	 8,	// 0x36 - Enable USB1 in S3
-	S33G,	 8,	// 0x37 - Enable 3G in S3
-	CMEM,	 32,	// 0x38 - CBMEM TOC
-	/* Integrated Graphics Device */
-	Offset (0x3c),
-	IGDS,	 8,	// 0x3c - IGD state (primary = 1)
-	TLST,	 8,	// 0x3d - Display Toggle List pointer
-	CADL,	 8,	// 0x3e - Currently Attached Devices List
-	PADL,	 8,	// 0x3f - Previously Attached Devices List
-	CSTE,	16,	// 0x40 - Current display state
-	NSTE,	16,	// 0x42 - Next display state
-	SSTE,	16,	// 0x44 - Set display state
-	Offset (0x46),
-	NDID,	 8,	// 0x46 - Number of Device IDs
-	DID1,	32,	// 0x47 - Device ID 1
-	DID2,	32,	// 0x4b - Device ID 2
-	DID3,	32,	// 0x4f - Device ID 3
-	DID4,	32,	// 0x53 - Device ID 4
-	DID5,	32,	// 0x57 - Device ID 5
-
-	/* TPM support */
-	Offset (0x5b),
-	TPMP,	 8,	// 0x5b - TPM Present
-	TPME,	 8,	// 0x5c - TPM Enable
-
-	/* LynxPoint Serial IO device BARs */
+	PCNT,	 8,	// 0x11 - Processor count
+	TPMP,	 8,	// 0x12 - TPM Present and Enabled
+
+	/* Device Config */
+	Offset (0x20),
+	S5U0,	 8,	// 0x20 - Enable USB0 in S5
+	S5U1,	 8,	// 0x21 - Enable USB1 in S5
+	S3U0,	 8,	// 0x22 - Enable USB0 in S3
+	S3U1,	 8,	// 0x23 - Enable USB1 in S3
+
+	/* Base addresses */
+	Offset (0x30),
+	CMEM,	 32,	// 0x30 - CBMEM TOC
+	TOLM,	 32,	// 0x34 - Top of Low Memory
+	CBMC,	 32,	// 0x38 - coreboot mem console pointer
+
+	/* Serial IO device BARs */
 	Offset (0x60),
 	S0B0,	32,	// 0x60 - D21:F0 Serial IO SDMA BAR0
 	S1B0,	32,	// 0x64 - D21:F1 Serial IO I2C0 BAR0
@@ -130,51 +83,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	S6B1,	32,	// 0x98 - D21:F6 Serial IO UAR1 BAR1
 	S7B1,	32,	// 0x9c - D23:F0 Serial IO SDIO BAR1
 
-	Offset (0xa0),
-	CBMC, 32,	// 0xa0 - coreboot mem console pointer
-
-	/* IGD OpRegion */
-	Offset (0xb4),
-	ASLB,	32,	// 0xb4 - IGD OpRegion Base Address
-	IBTT,	 8,	// 0xb8 - IGD boot panel device
-	IPAT,	 8,	// 0xb9 - IGD panel type cmos option
-	ITVF,	 8,	// 0xba - IGD TV format cmos option
-	ITVM,	 8,	// 0xbb - IGD TV minor format option
-	IPSC,	 8,	// 0xbc - IGD panel scaling
-	IBLC,	 8,	// 0xbd - IGD BLC config
-	IBIA,	 8,	// 0xbe - IGD BIA config
-	ISSC,	 8,	// 0xbf - IGD SSC config
-	I409,	 8,	// 0xc0 - IGD 0409 modified settings
-	I509,	 8,	// 0xc1 - IGD 0509 modified settings
-	I609,	 8,	// 0xc2 - IGD 0609 modified settings
-	I709,	 8,	// 0xc3 - IGD 0709 modified settings
-	IDMM,	 8,	// 0xc4 - IGD Power conservation feature
-	IDMS,	 8,	// 0xc5 - IGD DVMT memory size
-	IF1E,	 8,	// 0xc6 - IGD function 1 enable
-	HVCO,	 8,	// 0xc7 - IGD HPLL VCO
-	NXD1,	32,	// 0xc8 - IGD _DGS next DID1
-	NXD2,	32,	// 0xcc - IGD _DGS next DID2
-	NXD3,	32,	// 0xd0 - IGD _DGS next DID3
-	NXD4,	32,	// 0xd4 - IGD _DGS next DID4
-	NXD5,	32,	// 0xd8 - IGD _DGS next DID5
-	NXD6,	32,	// 0xdc - IGD _DGS next DID6
-	NXD7,	32,	// 0xe0 - IGD _DGS next DID7
-	NXD8,	32,	// 0xe4 - IGD _DGS next DID8
-
-	ISCI,	 8,	// 0xe8 - IGD SMI/SCI mode (0: SCI)
-	PAVP,	 8,	// 0xe9 - IGD PAVP data
-	Offset (0xeb),
-	OSCC,	 8,	// 0xeb - PCIe OSC control
-	NPCE,	 8,	// 0xec - native pcie support
-	PLFL,	 8,	// 0xed - platform flavor
-	BREV,	 8,	// 0xee - board revision
-	DPBM,	 8,	// 0xef - digital port b mode
-	DPCM,	 8,	// 0xf0 - digital port c mode
-	DPDM,	 8,	// 0xf1 - digital port d mode
-	ALFP,	 8,	// 0xf2 - active lfp
-	IMON,	 8,	// 0xf3 - current graphics turbo imon value
-	MMIO,	 8,	// 0xf4 - 64bit mmio support
-
 	/* ChromeOS specific */
 	Offset (0x100),
 	#include <vendorcode/google/chromeos/acpi/gnvs.asl>
@@ -207,78 +115,3 @@ Method (S5UD)
 	Store (Zero, \S5U0)
 	Store (Zero, \S5U1)
 }
-
-/* Set flag to enable 3G module in S3 */
-Method (S3GE)
-{
-	Store (One, \S33G)
-}
-
-/* Set flag to disable 3G module in S3 */
-Method (S3GD)
-{
-	Store (Zero, \S33G)
-}
-
-External (\_TZ.THRM)
-External (\_TZ.SKIN)
-
-Method (TZUP)
-{
-	/* Update Primary Thermal Zone */
-	If (CondRefOf (\_TZ.THRM, Local0)) {
-		Notify (\_TZ.THRM, 0x81)
-	}
-
-	/* Update Secondary Thermal Zone */
-	If (CondRefOf (\_TZ.SKIN, Local0)) {
-		Notify (\_TZ.SKIN, 0x81)
-	}
-}
-
-/* Update Fan 0 thresholds */
-Method (F0UT, 2)
-{
-	Store (Arg0, \F0OF)
-	Store (Arg1, \F0ON)
-	TZUP ()
-}
-
-/* Update Fan 1 thresholds */
-Method (F1UT, 2)
-{
-	Store (Arg0, \F1OF)
-	Store (Arg1, \F1ON)
-	TZUP ()
-}
-
-/* Update Fan 2 thresholds */
-Method (F2UT, 2)
-{
-	Store (Arg0, \F2OF)
-	Store (Arg1, \F2ON)
-	TZUP ()
-}
-
-/* Update Fan 3 thresholds */
-Method (F3UT, 2)
-{
-	Store (Arg0, \F3OF)
-	Store (Arg1, \F3ON)
-	TZUP ()
-}
-
-/* Update Fan 4 thresholds */
-Method (F4UT, 2)
-{
-	Store (Arg0, \F4OF)
-	Store (Arg1, \F4ON)
-	TZUP ()
-}
-
-/* Update Temperature Sensor ID */
-Method (TMPU, 1)
-{
-	Store (Arg0, \TMPS)
-	TZUP ()
-}
diff --git a/src/soc/intel/baytrail/baytrail/nvs.h b/src/soc/intel/baytrail/baytrail/nvs.h
index 4283ca13d5..e261e7cefc 100644
--- a/src/soc/intel/baytrail/baytrail/nvs.h
+++ b/src/soc/intel/baytrail/baytrail/nvs.h
@@ -34,97 +34,27 @@ typedef struct {
 	u32	p80d; /* 0x0b - Debug port (IO 0x80) value */
 	u8	lids; /* 0x0f - LID state (open = 1) */
 	u8	pwrs; /* 0x10 - Power state (AC = 1) */
-	/* Thermal policy */
-	u8	tlvl; /* 0x11 - Throttle Level Limit */
-	u8	flvl; /* 0x12 - Current FAN Level */
-	u8	tcrt; /* 0x13 - Critical Threshold */
-	u8	tpsv; /* 0x14 - Passive Threshold */
-	u8	tmax; /* 0x15 - CPU Tj_max */
-	u8	f0of; /* 0x16 - FAN 0 OFF Threshold */
-	u8	f0on; /* 0x17 - FAN 0 ON Threshold */
-	u8	f0pw; /* 0x18 - FAN 0 PWM value */
-	u8	f1of; /* 0x19 - FAN 1 OFF Threshold */
-	u8	f1on; /* 0x1a - FAN 1 ON Threshold */
-	u8	f1pw; /* 0x1b - FAN 1 PWM value */
-	u8	f2of; /* 0x1c - FAN 2 OFF Threshold */
-	u8	f2on; /* 0x1d - FAN 2 ON Threshold */
-	u8	f2pw; /* 0x1e - FAN 2 PWM value */
-	u8	f3of; /* 0x1f - FAN 3 OFF Threshold */
-	u8	f3on; /* 0x20 - FAN 3 ON Threshold */
-	u8	f3pw; /* 0x21 - FAN 3 PWM value */
-	u8	f4of; /* 0x22 - FAN 4 OFF Threshold */
-	u8	f4on; /* 0x23 - FAN 4 ON Threshold */
-	u8	f4pw; /* 0x24 - FAN 4 PWM value */
-	u8	tmps; /* 0x25 - Temperature Sensor ID */
-	u8	rsvd3[2];
-	/* Processor Identification */
-	u8	apic; /* 0x28 - APIC enabled */
-	u8	mpen; /* 0x29 - MP capable/enabled */
-	u8	pcp0; /* 0x2a - PDC CPU/CORE 0 */
-	u8	pcp1; /* 0x2b - PDC CPU/CORE 1 */
-	u8	ppcm; /* 0x2c - Max. PPC state */
-	u8      pcnt; /* 0x2d - Processor Count */
-	u8	rsvd4[4];
-	/* Super I/O & CMOS config */
-	u8	natp; /* 0x32 - SIO type */
-	u8	s5u0; /* 0x33 - Enable USB0 in S5 */
-	u8	s5u1; /* 0x34 - Enable USB1 in S5 */
-	u8	s3u0; /* 0x35 - Enable USB0 in S3 */
-	u8	s3u1; /* 0x36 - Enable USB1 in S3 */
-	u8	s33g; /* 0x37 - Enable S3 in 3G */
-	u32	cmem; /* 0x38 - CBMEM TOC */
-	/* Integrated Graphics Device */
-	u8	igds; /* 0x3c - IGD state */
-	u8	tlst; /* 0x3d - Display Toggle List Pointer */
-	u8	cadl; /* 0x3e - currently attached devices */
-	u8	padl; /* 0x3f - previously attached devices */
-	u16	cste; /* 0x40 - current display state */
-	u16	nste; /* 0x42 - next display state */
-	u16	sste; /* 0x44 - set display state */
-	u8	ndid; /* 0x46 - number of device ids */
-	u32	did[5]; /* 0x47 - 5b device id 1..5 */
-	/* TPM support */
-	u8	tpmp; /* 0x5b - TPM Present */
-	u8	tpme; /* 0x5c - TPM Enable */
-	u8	rsvd5[3];
-	/* LynxPoint Serial IO device BARs */
+	u8	pcnt; /* 0x11 - Processor Count */
+	u8	tpmp; /* 0x12 - TPM Present and Enabled */
+	u8	rsvd1[13];
+
+	/* Device Config */
+	u8	s5u0; /* 0x20 - Enable USB0 in S5 */
+	u8	s5u1; /* 0x21 - Enable USB1 in S5 */
+	u8	s3u0; /* 0x22 - Enable USB0 in S3 */
+	u8	s3u1; /* 0x23 - Enable USB1 in S3 */
+	u8	rsvd2[12];
+
+	/* Base Addresses */
+	u32	cmem; /* 0x30 - CBMEM TOC */
+	u32	tolm; /* 0x34 - Top of Low Memory */
+	u32	cbmc; /* 0x38 - coreboot memconsole */
+	u8	rsvd5[39];
+
+	/* Serial IO device BARs */
 	u32	s0b[8]; /* 0x60 - 0x7f - BAR0 */
 	u32	s1b[8]; /* 0x80 - 0x9f - BAR1 */
-	u32	cbmc;   /* 0xa0 - 0xa3 - coreboot memconsole */
-	u8	rsvd6[16];
-	/* IGD OpRegion (not implemented yet) */
-	u32	aslb; /* 0xb4 - IGD OpRegion Base Address */
-	u8	ibtt; /* 0xb8 - IGD boot type */
-	u8	ipat; /* 0xb9 - IGD panel type */
-	u8	itvf; /* 0xba - IGD TV format */
-	u8	itvm; /* 0xbb - IGD TV minor format */
-	u8	ipsc; /* 0xbc - IGD Panel Scaling */
-	u8	iblc; /* 0xbd - IGD BLC configuration */
-	u8	ibia; /* 0xbe - IGD BIA configuration */
-	u8	issc; /* 0xbf - IGD SSC configuration */
-	u8	i409; /* 0xc0 - IGD 0409 modified settings */
-	u8	i509; /* 0xc1 - IGD 0509 modified settings */
-	u8	i609; /* 0xc2 - IGD 0609 modified settings */
-	u8	i709; /* 0xc3 - IGD 0709 modified settings */
-	u8	idmm; /* 0xc4 - IGD Power Conservation */
-	u8	idms; /* 0xc5 - IGD DVMT memory size */
-	u8	if1e; /* 0xc6 - IGD Function 1 Enable */
-	u8	hvco; /* 0xc7 - IGD HPLL VCO */
-	u32	nxd[8]; /* 0xc8 - IGD next state DIDx for _DGS */
-	u8	isci; /* 0xe8 - IGD SMI/SCI mode (0: SCI) */
-	u8	pavp; /* 0xe9 - IGD PAVP data */
-	u8	rsvd12; /* 0xea - rsvd */
-	u8	oscc; /* 0xeb - PCIe OSC control */
-	u8	npce; /* 0xec - native pcie support */
-	u8	plfl; /* 0xed - platform flavor */
-	u8	brev; /* 0xee - board revision */
-	u8	dpbm; /* 0xef - digital port b mode */
-	u8	dpcm; /* 0xf0 - digital port c mode */
-	u8	dpdm; /* 0xf1 - digital port c mode */
-	u8	alfp; /* 0xf2 - active lfp */
-	u8	imon; /* 0xf3 - current graphics turbo imon value */
-	u8	mmio; /* 0xf4 - 64bit mmio support */
-	u8	rsvd13[11]; /* 0xf5 - rsvd */
+	u8	rsvd6[95];
 
 	/* ChromeOS specific (starts at 0x100)*/
 	chromeos_acpi_t chromeos;