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authorSridhar Siricilla <sridhar.siricilla@intel.com>2019-09-13 16:32:00 +0530
committerSubrata Banik <subrata.banik@intel.com>2020-08-13 05:44:24 +0000
commitb2353a7bdcaca6a6138e641ff1c5cfcbc7e6e799 (patch)
treebfea012fdebc45bf5a8e079d05b0892c21ddc4ea
parent77025b3f56ab599db70e923650eb6e42d84f267f (diff)
downloadcoreboot-b2353a7bdcaca6a6138e641ff1c5cfcbc7e6e799.tar.xz
soc/intel/common/block: Stitch CSE blobs into FW_MAIN_X partitions
Add Kconfig option for CSE me_rw blob path and stitch the me_rw blob into FW_MAIN_X partitions. BUG=b:145796136 Change-Id: I1d2908e9e16858c5f333e1b10b19d18b7ca27765 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35406 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/soc/intel/common/block/cse/Kconfig6
-rw-r--r--src/soc/intel/common/block/cse/Makefile.inc9
2 files changed, 15 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig
index b6f49c61e8..1cb7d35fb0 100644
--- a/src/soc/intel/common/block/cse/Kconfig
+++ b/src/soc/intel/common/block/cse/Kconfig
@@ -31,3 +31,9 @@ config SOC_INTEL_CSE_RW_CBFS_NAME
default "me_rw"
help
CBFS entry name for Intel CSE CBFS RW blob
+
+config SOC_INTEL_CSE_RW_FILE
+ string "Intel CSE CBFS RW path and filename"
+ default ""
+ help
+ Intel CSE CBFS RW blob path and file name
diff --git a/src/soc/intel/common/block/cse/Makefile.inc b/src/soc/intel/common/block/cse/Makefile.inc
index 30ff66bf6f..11cc3c20d1 100644
--- a/src/soc/intel/common/block/cse/Makefile.inc
+++ b/src/soc/intel/common/block/cse/Makefile.inc
@@ -3,3 +3,12 @@ romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c
ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c
ramstage-$(CONFIG_SOC_INTEL_CSE_LITE_SKU) += cse_lite.c
smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_IN_SMM) += disable_heci.c
+
+ifneq ($(CONFIG_SOC_INTEL_CSE_RW_FILE),"")
+CSE_LITE_ME_RW = $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_CBFS_NAME))
+regions-for-file-$(CSE_LITE_ME_RW) = FW_MAIN_A,FW_MAIN_B
+cbfs-files-y += $(CSE_LITE_ME_RW)
+$(CSE_LITE_ME_RW)-file := $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_FILE))
+$(CSE_LITE_ME_RW)-name := $(CSE_LITE_ME_RW)
+$(CSE_LITE_ME_RW)-type := raw
+endif