diff options
author | Stefan Reinauer <stepan@coresystems.de> | 2009-04-30 13:58:42 +0000 |
---|---|---|
committer | Stefan Reinauer <stepan@openbios.org> | 2009-04-30 13:58:42 +0000 |
commit | b5fb0c5c4eda2329d848aedcf4f7e8b6dc8012b2 (patch) | |
tree | 9a0897635ecbeab0dd64124cd165d3460174a359 | |
parent | 6841ce653741b3dafe8e3482b4a93adbaee53552 (diff) | |
download | coreboot-b5fb0c5c4eda2329d848aedcf4f7e8b6dc8012b2.tar.xz |
Add high tables support to all northbridges.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4238 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
33 files changed, 264 insertions, 30 deletions
diff --git a/src/northbridge/amd/amdfam10/Config.lb b/src/northbridge/amd/amdfam10/Config.lb index 5e9081991d..79b7b49280 100644 --- a/src/northbridge/amd/amdfam10/Config.lb +++ b/src/northbridge/amd/amdfam10/Config.lb @@ -19,8 +19,10 @@ uses AGP_APERTURE_SIZE uses HAVE_ACPI_TABLES +uses HAVE_HIGH_TABLES default AGP_APERTURE_SIZE=0x4000000 +default HAVE_HIGH_TABLES=1 config chip.h diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 92f9ea3819..6a9504ccc1 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -911,6 +911,11 @@ static void disable_hoist_memory(unsigned long hole_startk, int i) #endif +#if HAVE_HIGH_TABLES==1 +#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB +extern uint64_t high_tables_base, high_tables_size; +#endif + static void pci_domain_set_resources(device_t dev) { #if CONFIG_PCI_64BIT_PREF_MEM == 1 @@ -1084,6 +1089,15 @@ static void pci_domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; +#if HAVE_HIGH_TABLES==1 + if (i==0 && high_tables_base==0) { + /* Leave some space for ACPI, PIRQ and MP tables */ + high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024; + high_tables_size = HIGH_TABLES_SIZE * 1024; + printk_debug("(split)%xK table at =%08llx\n", HIGH_TABLES_SIZE, + high_tables_base); + } +#endif } #if CONFIG_AMDMCT == 0 #if HW_MEM_HOLE_SIZEK != 0 @@ -1108,6 +1122,15 @@ static void pci_domain_set_resources(device_t dev) } ram_resource(dev, (idx | i), basek, sizek); idx += 0x10; +#if HAVE_HIGH_TABLES==1 + printk_debug("%d: mmio_basek=%08lx, basek=%08x, limitk=%08x\n", + i, mmio_basek, basek, limitk); + if (i==0 && high_tables_base==0) { + /* Leave some space for ACPI, PIRQ and MP tables */ + high_tables_base = (limitk - HIGH_TABLES_SIZE) * 1024; + high_tables_size = HIGH_TABLES_SIZE * 1024; + } +#endif } for(link = 0; link < dev->links; link++) { diff --git a/src/northbridge/amd/gx1/Config.lb b/src/northbridge/amd/gx1/Config.lb index 16463e0ccd..adb96c3c64 100644 --- a/src/northbridge/amd/gx1/Config.lb +++ b/src/northbridge/amd/gx1/Config.lb @@ -1,2 +1,4 @@ +uses HAVE_HIGH_TABLES config chip.h driver northbridge.o +default HAVE_HIGH_TABLES=1 diff --git a/src/northbridge/amd/gx1/northbridge.c b/src/northbridge/amd/gx1/northbridge.c index 247c24304e..63cc003df0 100644 --- a/src/northbridge/amd/gx1/northbridge.c +++ b/src/northbridge/amd/gx1/northbridge.c @@ -126,6 +126,11 @@ static uint32_t find_pci_tolm(struct bus *bus) return tolm; } +#if HAVE_HIGH_TABLES==1 +#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB +extern uint64_t high_tables_base, high_tables_size; +#endif + static void pci_domain_set_resources(device_t dev) { device_t mc_dev; @@ -168,6 +173,13 @@ static void pci_domain_set_resources(device_t dev) */ tolmk = tomk; } + +#if HAVE_HIGH_TABLES==1 + /* Leave some space for ACPI, PIRQ and MP tables */ + high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024; + high_tables_size = HIGH_TABLES_SIZE * 1024; +#endif + /* Report the memory regions */ idx = 10; ram_resource(dev, idx++, 0, tolmk); diff --git a/src/northbridge/amd/gx2/Config.lb b/src/northbridge/amd/gx2/Config.lb index 4b361f5c90..342dac967c 100644 --- a/src/northbridge/amd/gx2/Config.lb +++ b/src/northbridge/amd/gx2/Config.lb @@ -1,5 +1,7 @@ +uses HAVE_HIGH_TABLES config chip.h driver northbridge.o object northbridgeinit.o object chipsetinit.o object grphinit.o +default HAVE_HIGH_TABLES=1 diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c index e285e52cb6..bfcef1af47 100644 --- a/src/northbridge/amd/gx2/northbridge.c +++ b/src/northbridge/amd/gx2/northbridge.c @@ -501,6 +501,11 @@ static struct device_operations cpu_bus_ops = { void chipsetInit (void); +#if HAVE_HIGH_TABLES==1 +#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB +extern uint64_t high_tables_base, high_tables_size; +#endif + static void enable_dev(struct device *dev) { printk_debug("gx2 north: enable_dev\n"); @@ -512,6 +517,7 @@ static void enable_dev(struct device *dev) if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) { struct northbridge_amd_gx2_config *nb = (struct northbridge_amd_gx2_config *)dev->chip_info; extern void cpubug(void); + u32 tomk; printk_debug("DEVICE_PATH_PCI_DOMAIN\n"); /* cpubug MUST be called before setup_gx2(), so we force the issue here */ northbridgeinit(); @@ -524,7 +530,13 @@ static void enable_dev(struct device *dev) graphics_init(); dev->ops = &pci_domain_ops; pci_set_method(dev); - ram_resource(dev, 0, 0, ((sizeram() - VIDEO_MB) * 1024) - SMM_SIZE); + tomk = ((sizeram() - VIDEO_MB) * 1024) - SMM_SIZE; +#if HAVE_HIGH_TABLES==1 + /* Leave some space for ACPI, PIRQ and MP tables */ + high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; + high_tables_size = HIGH_TABLES_SIZE * 1024; +#endif + ram_resource(dev, 0, 0, tomk); } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) { printk_debug("DEVICE_PATH_APIC_CLUSTER\n"); dev->ops = &cpu_bus_ops; diff --git a/src/northbridge/amd/lx/Config.lb b/src/northbridge/amd/lx/Config.lb index 9b1d4c2c71..b9388893ab 100644 --- a/src/northbridge/amd/lx/Config.lb +++ b/src/northbridge/amd/lx/Config.lb @@ -1,4 +1,6 @@ +uses HAVE_HIGH_TABLES config chip.h driver northbridge.o object northbridgeinit.o object grphinit.o +default HAVE_HIGH_TABLES=1 diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c index 9762510cf4..390c94cf78 100644 --- a/src/northbridge/amd/lx/northbridge.c +++ b/src/northbridge/amd/lx/northbridge.c @@ -415,19 +415,32 @@ static void ram_resource(device_t dev, unsigned long index, IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; } +#if HAVE_HIGH_TABLES==1 +#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB +extern uint64_t high_tables_base, high_tables_size; +#endif + static void pci_domain_set_resources(device_t dev) { int idx; + u32 tomk; device_t mc_dev; printk_spew(">> Entering northbridge.c: %s\n", __func__); mc_dev = dev->link[0].children; if (mc_dev) { + tomk = get_systop() / 1024; /* Report the memory regions */ idx = 10; ram_resource(dev, idx++, 0, 640); - ram_resource(dev, idx++, 1024, (get_systop() - 0x100000) / 1024); // Systop - 1 MB -> KB + ram_resource(dev, idx++, 1024, tomk - 1024); // Systop - 1 MB -> KB + +#if HAVE_HIGH_TABLES==1 + /* Leave some space for ACPI, PIRQ and MP tables */ + high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; + high_tables_size = HIGH_TABLES_SIZE * 1024; +#endif } assign_resources(&dev->link[0]); diff --git a/src/northbridge/intel/e7501/Config.lb b/src/northbridge/intel/e7501/Config.lb index 59154f7ed3..2a8095f692 100644 --- a/src/northbridge/intel/e7501/Config.lb +++ b/src/northbridge/intel/e7501/Config.lb @@ -1,3 +1,7 @@ +uses HAVE_HIGH_TABLES + config chip.h object northbridge.o + +default HAVE_HIGH_TABLES=1 diff --git a/src/northbridge/intel/e7501/northbridge.c b/src/northbridge/intel/e7501/northbridge.c index b1d553aab1..7168bf3112 100644 --- a/src/northbridge/intel/e7501/northbridge.c +++ b/src/northbridge/intel/e7501/northbridge.c @@ -65,6 +65,11 @@ static uint32_t find_pci_tolm(struct bus *bus) return tolm; } +#if HAVE_HIGH_TABLES==1 +#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB +extern uint64_t high_tables_base, high_tables_size; +#endif + static void pci_domain_set_resources(device_t dev) { device_t mc_dev; @@ -140,6 +145,12 @@ static void pci_domain_set_resources(device_t dev) ram_resource(dev, idx++, remapbasek, (remaplimitk + 64*1024) - remapbasek); } + +#if HAVE_HIGH_TABLES==1 + /* Leave some space for ACPI, PIRQ and MP tables */ + high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024; + high_tables_size = HIGH_TABLES_SIZE * 1024; +#endif } assign_resources(&dev->link[0]); } diff --git a/src/northbridge/intel/e7520/Config.lb b/src/northbridge/intel/e7520/Config.lb index 064c867618..03a78974d4 100644 --- a/src/northbridge/intel/e7520/Config.lb +++ b/src/northbridge/intel/e7520/Config.lb @@ -1,3 +1,5 @@ +uses HAVE_HIGH_TABLES + config chip.h driver northbridge.o driver pciexp_porta.o @@ -5,6 +7,8 @@ driver pciexp_porta1.o driver pciexp_portb.o driver pciexp_portc.o +default HAVE_HIGH_TABLES=1 + makerule raminit_test depends "$(TOP)/src/northbridge/intel/e7520/raminit_test.c" depends "$(TOP)/src/northbridge/intel/e7520/raminit.c" diff --git a/src/northbridge/intel/e7520/northbridge.c b/src/northbridge/intel/e7520/northbridge.c index ad44c9b5e6..f2b2a0f3a0 100644 --- a/src/northbridge/intel/e7520/northbridge.c +++ b/src/northbridge/intel/e7520/northbridge.c @@ -76,6 +76,10 @@ static uint32_t find_pci_tolm(struct bus *bus) return tolm; } +#if HAVE_HIGH_TABLES==1 +#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB +extern uint64_t high_tables_base, high_tables_size; +#endif static void pci_domain_set_resources(device_t dev) { @@ -164,6 +168,12 @@ static void pci_domain_set_resources(device_t dev) ram_resource(dev, 6, remapbasek, (remaplimitk + 64*1024) - remapbasek); } + +#if HAVE_HIGH_TABLES==1 + /* Leave some space for ACPI, PIRQ and MP tables */ + high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024; + high_tables_size = HIGH_TABLES_SIZE * 1024; +#endif } assign_resources(&dev->link[0]); } diff --git a/src/northbridge/intel/e7525/Config.lb b/src/northbridge/intel/e7525/Config.lb index 919e0f8adf..07930ff434 100644 --- a/src/northbridge/intel/e7525/Config.lb +++ b/src/northbridge/intel/e7525/Config.lb @@ -1,3 +1,5 @@ +uses HAVE_HIGH_TABLES + config chip.h driver northbridge.o driver pciexp_porta.o @@ -5,6 +7,8 @@ driver pciexp_porta1.o driver pciexp_portb.o driver pciexp_portc.o +default HAVE_HIGH_TABLES=1 + makerule raminit_test depends "$(TOP)/src/northbridge/intel/e7525/raminit_test.c" depends "$(TOP)/src/northbridge/intel/e7525/raminit.c" diff --git a/src/northbridge/intel/e7525/northbridge.c b/src/northbridge/intel/e7525/northbridge.c index 2ed8922339..7900129ec2 100644 --- a/src/northbridge/intel/e7525/northbridge.c +++ b/src/northbridge/intel/e7525/northbridge.c @@ -76,6 +76,10 @@ static uint32_t find_pci_tolm(struct bus *bus) return tolm; } +#if HAVE_HIGH_TABLES==1 +#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB +extern uint64_t high_tables_base, high_tables_size; +#endif static void pci_domain_set_resources(device_t dev) { @@ -164,6 +168,12 @@ static void pci_domain_set_resources(device_t dev) ram_resource(dev, 6, remapbasek, (remaplimitk + 64*1024) - remapbasek); } + +#if HAVE_HIGH_TABLES==1 + /* Leave some space for ACPI, PIRQ and MP tables */ + high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024; + high_tables_size = HIGH_TABLES_SIZE * 1024; +#endif } assign_resources(&dev->link[0]); } diff --git a/src/northbridge/intel/i3100/Config.lb b/src/northbridge/intel/i3100/Config.lb index ea4c8eb728..1534605dc0 100644 --- a/src/northbridge/intel/i3100/Config.lb +++ b/src/northbridge/intel/i3100/Config.lb @@ -17,6 +17,11 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +uses HAVE_HIGH_TABLES + config chip.h + driver northbridge.o driver pciexp_porta.o + +default HAVE_HIGH_TABLES=1 diff --git a/src/northbridge/intel/i3100/northbridge.c b/src/northbridge/intel/i3100/northbridge.c index d36af7caae..928fe94c73 100644 --- a/src/northbridge/intel/i3100/northbridge.c +++ b/src/northbridge/intel/i3100/northbridge.c @@ -97,6 +97,10 @@ static u32 find_pci_tolm(struct bus *bus) return tolm; } +#if HAVE_HIGH_TABLES==1 +#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB +extern uint64_t high_tables_base, high_tables_size; +#endif static void pci_domain_set_resources(device_t dev) { @@ -185,6 +189,12 @@ static void pci_domain_set_resources(device_t dev) ram_resource(dev, 6, remapbasek, (remaplimitk + 64*1024) - remapbasek); } + +#if HAVE_HIGH_TABLES==1 + /* Leave some space for ACPI, PIRQ and MP tables */ + high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024; + high_tables_size = HIGH_TABLES_SIZE * 1024; +#endif } assign_resources(&dev->link[0]); } diff --git a/src/northbridge/intel/i440bx/Config.lb b/src/northbridge/intel/i440bx/Config.lb index 82a05ee265..c9a26b08b3 100644 --- a/src/northbridge/intel/i440bx/Config.lb +++ b/src/northbridge/intel/i440bx/Config.lb @@ -18,5 +18,10 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +uses HAVE_HIGH_TABLES + config chip.h + driver northbridge.o + +default HAVE_HIGH_TABLES=1 diff --git a/src/northbridge/intel/i440bx/northbridge.c b/src/northbridge/intel/i440bx/northbridge.c index 306e73e66d..f95a1a7597 100644 --- a/src/northbridge/intel/i440bx/northbridge.c +++ b/src/northbridge/intel/i440bx/northbridge.c @@ -91,6 +91,10 @@ static uint32_t find_pci_tolm(struct bus *bus) return tolm; } +#if HAVE_HIGH_TABLES==1 +#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB +extern uint64_t high_tables_base, high_tables_size; +#endif static void pci_domain_set_resources(device_t dev) { device_t mc_dev; @@ -127,6 +131,12 @@ static void pci_domain_set_resources(device_t dev) idx = 10; ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 768, tolmk - 768); + +#if HAVE_HIGH_TABLES==1 + /* Leave some space for ACPI, PIRQ and MP tables */ + high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; + high_tables_size = HIGH_TABLES_SIZE * 1024; +#endif } assign_resources(&dev->link[0]); diff --git a/src/northbridge/intel/i82810/Config.lb b/src/northbridge/intel/i82810/Config.lb index e8d57b2fb8..04375d89c1 100644 --- a/src/northbridge/intel/i82810/Config.lb +++ b/src/northbridge/intel/i82810/Config.lb @@ -18,5 +18,10 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +uses HAVE_HIGH_TABLES + config chip.h + driver northbridge.o + +default HAVE_HIGH_TABLES=1 diff --git a/src/northbridge/intel/i82810/northbridge.c b/src/northbridge/intel/i82810/northbridge.c index eb8a657982..bfbd338069 100644 --- a/src/northbridge/intel/i82810/northbridge.c +++ b/src/northbridge/intel/i82810/northbridge.c @@ -122,6 +122,11 @@ static int translate_i82810_to_mb[] = { /* MB */0, 8, 0, 16, 16, 24, 32, 32, 48, 64, 64, 96, 128, 128, 192, 256, }; +#if HAVE_HIGH_TABLES==1 +#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB +extern uint64_t high_tables_base, high_tables_size; +#endif + static void pci_domain_set_resources(device_t dev) { device_t mc_dev; @@ -166,6 +171,12 @@ static void pci_domain_set_resources(device_t dev) idx = 10; ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 1024, tolmk - 1024); + +#if HAVE_HIGH_TABLES==1 + /* Leave some space for ACPI, PIRQ and MP tables */ + high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; + high_tables_size = HIGH_TABLES_SIZE * 1024; +#endif } assign_resources(&dev->link[0]); } diff --git a/src/northbridge/intel/i82830/Config.lb b/src/northbridge/intel/i82830/Config.lb index d2ccd5d926..f55eab27fd 100644 --- a/src/northbridge/intel/i82830/Config.lb +++ b/src/northbridge/intel/i82830/Config.lb @@ -18,5 +18,10 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +uses HAVE_HIGH_TABLES + config chip.h + driver northbridge.o + +default HAVE_HIGH_TABLES=1 diff --git a/src/northbridge/intel/i82830/northbridge.c b/src/northbridge/intel/i82830/northbridge.c index 689bf19bc2..bf79ecdca1 100644 --- a/src/northbridge/intel/i82830/northbridge.c +++ b/src/northbridge/intel/i82830/northbridge.c @@ -107,6 +107,10 @@ static uint32_t find_pci_tolm(struct bus *bus) return tolm; } +#if HAVE_HIGH_TABLES==1 +#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB +extern uint64_t high_tables_base, high_tables_size; +#endif static void pci_domain_set_resources(device_t dev) { device_t mc_dev; @@ -144,6 +148,12 @@ static void pci_domain_set_resources(device_t dev) idx = 10; ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 1024, tolmk - 1024); + +#if HAVE_HIGH_TABLES==1 + /* Leave some space for ACPI, PIRQ and MP tables */ + high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; + high_tables_size = HIGH_TABLES_SIZE * 1024; +#endif } assign_resources(&dev->link[0]); } diff --git a/src/northbridge/intel/i855gme/Config.lb b/src/northbridge/intel/i855gme/Config.lb index 5a7cd14600..83edd47783 100644 --- a/src/northbridge/intel/i855gme/Config.lb +++ b/src/northbridge/intel/i855gme/Config.lb @@ -18,7 +18,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +uses HAVE_HIGH_TABLES + config chip.h + object northbridge.o -#driver misc_control.o +default HAVE_HIGH_TABLES=1 diff --git a/src/northbridge/intel/i855gme/northbridge.c b/src/northbridge/intel/i855gme/northbridge.c index e5fecf16ee..ec42c6eb73 100644 --- a/src/northbridge/intel/i855gme/northbridge.c +++ b/src/northbridge/intel/i855gme/northbridge.c @@ -88,6 +88,10 @@ static uint32_t find_pci_tolm(struct bus *bus) return tolm; } +#if HAVE_HIGH_TABLES==1 +#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB +extern uint64_t high_tables_base, high_tables_size; +#endif static void pci_domain_set_resources(device_t dev) { device_t mc_dev; @@ -143,6 +147,11 @@ static void pci_domain_set_resources(device_t dev) /* ram_resource(dev, idx++, 1024, tolmk - 1024); */ ram_resource(dev, idx++, 768, tolmk - 768); +#if HAVE_HIGH_TABLES==1 + /* Leave some space for ACPI, PIRQ and MP tables */ + high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; + high_tables_size = HIGH_TABLES_SIZE * 1024; +#endif } assign_resources(&dev->link[0]); } diff --git a/src/northbridge/intel/i855pm/Config.lb b/src/northbridge/intel/i855pm/Config.lb index f101a921fd..2a8095f692 100644 --- a/src/northbridge/intel/i855pm/Config.lb +++ b/src/northbridge/intel/i855pm/Config.lb @@ -1,4 +1,7 @@ +uses HAVE_HIGH_TABLES + config chip.h + object northbridge.o -#driver misc_control.o +default HAVE_HIGH_TABLES=1 diff --git a/src/northbridge/intel/i855pm/northbridge.c b/src/northbridge/intel/i855pm/northbridge.c index 60648542ae..4fbd3b3cec 100644 --- a/src/northbridge/intel/i855pm/northbridge.c +++ b/src/northbridge/intel/i855pm/northbridge.c @@ -66,6 +66,11 @@ static uint32_t find_pci_tolm(struct bus *bus) return tolm; } +#if HAVE_HIGH_TABLES==1 +#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB +extern uint64_t high_tables_base, high_tables_size; +#endif + static void pci_domain_set_resources(device_t dev) { device_t mc_dev; @@ -108,6 +113,12 @@ static void pci_domain_set_resources(device_t dev) idx = 10; ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 768, tolmk - 768); + +#if HAVE_HIGH_TABLES==1 + /* Leave some space for ACPI, PIRQ and MP tables */ + high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; + high_tables_size = HIGH_TABLES_SIZE * 1024; +#endif } assign_resources(&dev->link[0]); } diff --git a/src/northbridge/via/cn700/Config.lb b/src/northbridge/via/cn700/Config.lb index 6a0b60cfe0..b824a17b75 100644 --- a/src/northbridge/via/cn700/Config.lb +++ b/src/northbridge/via/cn700/Config.lb @@ -18,8 +18,14 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +uses HAVE_HIGH_TABLES + config chip.h + object vgabios.o + driver northbridge.o driver agp.o driver vga.o + +default HAVE_HIGH_TABLES=1 diff --git a/src/northbridge/via/cn700/northbridge.c b/src/northbridge/via/cn700/northbridge.c index af914528d9..2d3adf1288 100644 --- a/src/northbridge/via/cn700/northbridge.c +++ b/src/northbridge/via/cn700/northbridge.c @@ -163,6 +163,12 @@ static u32 find_pci_tolm(struct bus *bus) return tolm; } +#if HAVE_HIGH_TABLES==1 +/* maximum size of high tables in KB */ +#define HIGH_TABLES_SIZE 64 +extern uint64_t high_tables_base, high_tables_size; +#endif + static void pci_domain_set_resources(device_t dev) { /* The order is important to find the correct RAM size. */ @@ -199,6 +205,13 @@ static void pci_domain_set_resources(device_t dev) /* The PCI hole does does not overlap the memory. */ tolmk = tomk; } + +#if HAVE_HIGH_TABLES == 1 + high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024; + high_tables_size = HIGH_TABLES_SIZE* 1024; + printk_debug("tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size); +#endif + /* Report the memory regions. */ idx = 10; /* TODO: Hole needed? */ diff --git a/src/northbridge/via/cx700/northbridge.c b/src/northbridge/via/cx700/northbridge.c index 11c98da2ca..c7bbb8bf85 100644 --- a/src/northbridge/via/cx700/northbridge.c +++ b/src/northbridge/via/cx700/northbridge.c @@ -123,12 +123,6 @@ static void pci_domain_set_resources(device_t dev) else tomk = (((rambits << 6) - (4 << reg) - 1) * 1024); -#if HAVE_HIGH_TABLES == 1 - high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; - high_tables_size = HIGH_TABLES_SIZE* 1024; - printk_debug("tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size); -#endif - /* Compute the top of Low memory */ tolmk = pci_tolm >> 10; if (tolmk >= tomk) { @@ -137,6 +131,12 @@ static void pci_domain_set_resources(device_t dev) tolmk -= 1024; // TOP 1M SM Memory } +#if HAVE_HIGH_TABLES == 1 + high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024; + high_tables_size = HIGH_TABLES_SIZE* 1024; + printk_debug("tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size); +#endif + /* Report the memory regions */ idx = 10; diff --git a/src/northbridge/via/vt8601/Config.lb b/src/northbridge/via/vt8601/Config.lb index 16463e0ccd..9cf0154983 100644 --- a/src/northbridge/via/vt8601/Config.lb +++ b/src/northbridge/via/vt8601/Config.lb @@ -1,2 +1,7 @@ +uses HAVE_HIGH_TABLES + config chip.h + driver northbridge.o + +default HAVE_HIGH_TABLES=1 diff --git a/src/northbridge/via/vt8601/northbridge.c b/src/northbridge/via/vt8601/northbridge.c index 5347017ddf..b1e1c494cb 100644 --- a/src/northbridge/via/vt8601/northbridge.c +++ b/src/northbridge/via/vt8601/northbridge.c @@ -101,6 +101,12 @@ static uint32_t find_pci_tolm(struct bus *bus) return tolm; } +#if HAVE_HIGH_TABLES==1 +/* maximum size of high tables in KB */ +#define HIGH_TABLES_SIZE 64 +extern uint64_t high_tables_base, high_tables_size; +#endif + static void pci_domain_set_resources(device_t dev) { static const uint8_t ramregs[] = { @@ -140,6 +146,13 @@ static void pci_domain_set_resources(device_t dev) */ tolmk = tomk; } + +#if HAVE_HIGH_TABLES == 1 + high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024; + high_tables_size = HIGH_TABLES_SIZE* 1024; + printk_debug("tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size); +#endif + /* Report the memory regions */ idx = 10; ram_resource(dev, idx++, 0, tolmk); diff --git a/src/northbridge/via/vt8623/Config.lb b/src/northbridge/via/vt8623/Config.lb index 16463e0ccd..9cf0154983 100644 --- a/src/northbridge/via/vt8623/Config.lb +++ b/src/northbridge/via/vt8623/Config.lb @@ -1,2 +1,7 @@ +uses HAVE_HIGH_TABLES + config chip.h + driver northbridge.o + +default HAVE_HIGH_TABLES=1 diff --git a/src/northbridge/via/vt8623/northbridge.c b/src/northbridge/via/vt8623/northbridge.c index 80a314c18a..70ba59c1d2 100644 --- a/src/northbridge/via/vt8623/northbridge.c +++ b/src/northbridge/via/vt8623/northbridge.c @@ -15,25 +15,11 @@ #include "northbridge.h" /* - * This fixup is based on capturing values from an Award bios. Without + * This fixup is based on capturing values from an Award BIOS. Without * this fixup the DMA write performance is awful (i.e. hdparm -t /dev/hda is 20x * slower than normal, ethernet drops packets). * Apparently these registers govern some sort of bus master behavior. */ -#if 0 -static void dump_dev(device_t dev) -{ - int i,j; - - for(i = 0; i < 256; i += 16) { - printk_debug("0x%x: ", i); - for(j = 0; j < 16; j++) { - printk_debug("%02x ", pci_read_config8(dev, i+j)); - } - printk_debug("\n"); - } -} -#endif static void northbridge_init(device_t dev) { @@ -72,7 +58,6 @@ static void northbridge_init(device_t dev) pci_write_config8(dev, 0xe0, c); pci_write_config8(dev, 0xe2, 0x42); /* 'cos award does */ } - //dump_dev(dev); } static void nullfunc(){} @@ -100,7 +85,6 @@ static void agp_init(device_t dev) pci_write_config8(dev, 0x43, 0x44); pci_write_config8(dev, 0x44, 0x34); pci_write_config8(dev, 0x83, 0x02); - //dump_dev(dev); } static struct device_operations agp_operations = { @@ -129,8 +113,6 @@ static void vga_init(device_t dev) pci_write_config32(dev,0x10,0xd8000008); pci_write_config32(dev,0x14,0xdc000000); - //dump_dev(dev); - // set up performnce counters for debugging vga init sequence //setup.lo = 0x1c0; // count instructions //wrmsr(0x187,setup); @@ -175,7 +157,6 @@ static void vga_init(device_t dev) #endif - pci_write_config32(dev,0x30,0); /* Set the vga mtrrs - disable for the moment as the add_var_mtrr function has vapourised */ @@ -272,6 +253,12 @@ static uint32_t find_pci_tolm(struct bus *bus) return tolm; } +#if HAVE_HIGH_TABLES==1 +/* maximum size of high tables in KB */ +#define HIGH_TABLES_SIZE 64 +extern uint64_t high_tables_base, high_tables_size; +#endif + static void pci_domain_set_resources(device_t dev) { static const uint8_t ramregs[] = {0x5a, 0x5b, 0x5c, 0x5d }; @@ -311,6 +298,13 @@ static void pci_domain_set_resources(device_t dev) */ tolmk = tomk; } + +#if HAVE_HIGH_TABLES == 1 + high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024; + high_tables_size = HIGH_TABLES_SIZE* 1024; + printk_debug("tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size); +#endif + /* Report the memory regions */ idx = 10; ram_resource(dev, idx++, 0, 640); /* first 640k */ |