diff options
author | CK Hu <ck.hu@mediatek.com> | 2020-05-11 16:27:53 +0800 |
---|---|---|
committer | Hung-Te Lin <hungte@chromium.org> | 2020-08-28 04:44:56 +0000 |
commit | ba616438e9e81355eb447034fc3159c6db80a69b (patch) | |
tree | ec2b9fa84480d221262ba9acda693f9cbff74216 | |
parent | a662648a7fbfc04bb0f4a2ef92d7faa4fb8c7e09 (diff) | |
download | coreboot-ba616438e9e81355eb447034fc3159c6db80a69b.tar.xz |
soc/mediatek/mt8192: Use SPI-NOR as flash controller
Add a SPI-NOR flash controller which supports pio mode.
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Change-Id: I1e38672a532dd8234b3ef24c84113888c8795810
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
-rw-r--r-- | src/soc/mediatek/mt8192/Makefile.inc | 4 | ||||
-rw-r--r-- | src/soc/mediatek/mt8192/flash_controller.c | 172 | ||||
-rw-r--r-- | src/soc/mediatek/mt8192/include/soc/flash_controller.h | 78 | ||||
-rw-r--r-- | src/soc/mediatek/mt8192/spi.c | 11 |
4 files changed, 265 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 2a825fbdec..01db141950 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -1,6 +1,7 @@ ifeq ($(CONFIG_SOC_MEDIATEK_MT8192),y) bootblock-y += bootblock.c +bootblock-y += flash_controller.c bootblock-y += ../common/gpio.c gpio.c bootblock-y += ../common/mmu_operations.c bootblock-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c @@ -8,6 +9,7 @@ bootblock-y += ../common/timer.c bootblock-y += ../common/uart.c bootblock-y += ../common/wdt.c +verstage-y += flash_controller.c verstage-y += ../common/gpio.c gpio.c verstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c verstage-y += ../common/timer.c @@ -15,11 +17,13 @@ verstage-y += ../common/uart.c romstage-y += ../common/cbmem.c romstage-y += emi.c +romstage-y += flash_controller.c romstage-y += ../common/gpio.c gpio.c romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c romstage-y += ../common/timer.c romstage-y += ../common/uart.c +ramstage-y += flash_controller.c ramstage-y += ../common/gpio.c gpio.c ramstage-y += emi.c ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c diff --git a/src/soc/mediatek/mt8192/flash_controller.c b/src/soc/mediatek/mt8192/flash_controller.c new file mode 100644 index 0000000000..304e4c353e --- /dev/null +++ b/src/soc/mediatek/mt8192/flash_controller.c @@ -0,0 +1,172 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <console/console.h> +#include <device/mmio.h> +#include <soc/flash_controller.h> +#include <spi_flash.h> +#include <spi-generic.h> +#include <stdint.h> +#include <string.h> +#include <timer.h> +#include <types.h> + +#define GET_NTH_BYTE(d, n) ((d >> (8 * n)) & 0xff) + +static int polling_cmd(u32 val) +{ + struct stopwatch sw; + + stopwatch_init_usecs_expire(&sw, SFLASH_POLLINGREG_US); + + while ((read32(&mt8192_nor->cmd) & val) != 0) { + if (stopwatch_expired(&sw)) + return -1; + } + + return 0; +} + +static int mt8192_nor_execute_cmd(u8 cmdval) +{ + u8 val = cmdval & ~SFLASH_AUTOINC; + + write8(&mt8192_nor->cmd, cmdval); + return polling_cmd(val); +} + +static int sflashhw_read_flash_status(u8 *value) +{ + if (mt8192_nor_execute_cmd(SFLASH_READSTATUS)) + return -1; + + *value = read8(&mt8192_nor->rdsr); + return 0; +} + +static int wait_for_write_done(void) +{ + struct stopwatch sw; + u8 reg; + + stopwatch_init_usecs_expire(&sw, SFLASH_POLLINGREG_US); + + while (sflashhw_read_flash_status(®) == 0) { + if (!(reg & SFLASH_WRITE_IN_PROGRESS)) + return 0; + if (stopwatch_expired(&sw)) + return -1; + } + + return -1; +} + +/* set serial flash program address */ +static void set_sfpaddr(u32 addr) +{ + write8(&mt8192_nor->radr[2], GET_NTH_BYTE(addr, 2)); + write8(&mt8192_nor->radr[1], GET_NTH_BYTE(addr, 1)); + write8(&mt8192_nor->radr[0], GET_NTH_BYTE(addr, 0)); +} + +static int sector_erase(int offset) +{ + if (wait_for_write_done()) + return -1; + + write8(&mt8192_nor->prgdata[5], SFLASH_OP_WREN); + write8(&mt8192_nor->cnt, 8); + mt8192_nor_execute_cmd(SFLASH_PRG_CMD); + + write8(&mt8192_nor->prgdata[5], SECTOR_ERASE_CMD); + write8(&mt8192_nor->prgdata[4], GET_NTH_BYTE(offset, 2)); + write8(&mt8192_nor->prgdata[3], GET_NTH_BYTE(offset, 1)); + write8(&mt8192_nor->prgdata[2], GET_NTH_BYTE(offset, 0)); + write8(&mt8192_nor->cnt, 32); + mt8192_nor_execute_cmd(SFLASH_PRG_CMD); + + if (wait_for_write_done()) + return -1; + + return 0; +} + +static int pio_read(u32 addr, u8 *buf, u32 len) +{ + set_sfpaddr(addr); + while (len) { + if (mt8192_nor_execute_cmd(SFLASH_RD_TRIGGER | SFLASH_AUTOINC)) + return -1; + + *buf++ = read8(&mt8192_nor->rdata); + len--; + } + return 0; +} + +static int nor_read(const struct spi_flash *flash, u32 addr, size_t len, + void *buf) +{ + if (pio_read(addr, buf, len)) + return -1; + + return 0; +} + +static int nor_write(const struct spi_flash *flash, u32 addr, size_t len, + const void *buf) +{ + const u8 *buffer = (const u8 *)buf; + + set_sfpaddr(addr); + while (len) { + write8(&mt8192_nor->wdata, *buffer); + if (mt8192_nor_execute_cmd(SFLASH_WR_TRIGGER | SFLASH_AUTOINC)) + return -1; + + if (wait_for_write_done()) + return -1; + buffer++; + len--; + } + return 0; +} + +static int nor_erase(const struct spi_flash *flash, u32 offset, size_t len) +{ + int sector_start = offset; + int sector_num = (u32)len / flash->sector_size; + + while (sector_num) { + if (!sector_erase(sector_start)) { + sector_start += flash->sector_size; + sector_num--; + } else { + printk(BIOS_WARNING, "Erase failed at %#x!\n", + sector_start); + return -1; + } + } + return 0; +} + +const struct spi_flash_ops spi_flash_ops = { + .read = nor_read, + .write = nor_write, + .erase = nor_erase, +}; + +int mtk_spi_flash_probe(const struct spi_slave *spi, + struct spi_flash *flash) +{ + write32(&mt8192_nor->wrprot, SFLASH_COMMAND_ENABLE); + memcpy(&flash->spi, spi, sizeof(*spi)); + + flash->sector_size = 0x1000; + flash->erase_cmd = SECTOR_ERASE_CMD; + flash->size = CONFIG_ROM_SIZE; + + flash->ops = &spi_flash_ops; + + return 0; +} diff --git a/src/soc/mediatek/mt8192/include/soc/flash_controller.h b/src/soc/mediatek/mt8192/include/soc/flash_controller.h new file mode 100644 index 0000000000..5655a9c001 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/flash_controller.h @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8192_FLASH_CONTROLLER_H__ +#define __SOC_MEDIATEK_MT8192_FLASH_CONTROLLER_H__ + +#include <spi-generic.h> +#include <stdint.h> +#include <soc/addressmap.h> + +enum { + SFLASH_POLLINGREG_US = 500000, + SFLASH_WRBUF_SIZE = 128, + SFLASHNAME_LENGTH = 16, + SFLASH_WRITE_IN_PROGRESS = 1, + SFLASH_COMMAND_ENABLE = 0x30, + SFLASH_DMA_ALIGN = 0x10, + + /* NOR flash controller commands */ + SFLASH_RD_TRIGGER = 1 << 0, + SFLASH_READSTATUS = 1 << 1, + SFLASH_PRG_CMD = 1 << 2, + SFLASH_WR_TRIGGER = 1 << 4, + SFLASH_WRITESTATUS = 1 << 5, + SFLASH_AUTOINC = 1 << 7, + /* NOR flash commands */ + SFLASH_OP_WREN = 0x6, + SECTOR_ERASE_CMD = 0x20, + SFLASH_UNPROTECTED = 0x0, + /* DMA commands */ + SFLASH_DMA_TRIGGER = 1 << 0, + SFLASH_DMA_SW_RESET = 1 << 1, + SFLASH_DMA_WDLE_EN = 1 << 2 +}; + +/* register Offset */ +struct mt8192_nor_regs { + u32 cmd; + u32 cnt; + u32 rdsr; + u32 rdata; + u32 radr[3]; + u32 wdata; + u32 prgdata[6]; + u32 shreg[10]; + u32 cfg[2]; + u32 shreg10; + u32 status[5]; + u32 timing; + u32 flash_cfg; + u32 reserved2[3]; + u32 sf_time; + u32 reserved3; + u32 diff_addr; + u32 del_sel[2]; + u32 intrstus; + u32 intren; + u32 pp_ctl; + u32 cfg3; + u32 chksum_ctl; + u32 chksum; + u32 aaicmd; + u32 wrprot; + u32 radr3; + u32 read_dual; + u32 delsel[3]; + u32 reserved[397]; + u32 cfg1_bri[2]; + u32 fdma_ctl; + u32 fdma_fadr; + u32 fdma_dadr; + u32 fdma_end_dadr; +}; +check_member(mt8192_nor_regs, fdma_end_dadr, 0x724); +static struct mt8192_nor_regs *const mt8192_nor = (void *)SFLASH_REG_BASE; + +int mtk_spi_flash_probe(const struct spi_slave *spi, struct spi_flash *flash); + +#endif /* __SOC_MEDIATEK_MT8192_FLASH_CONTROLLER_H__ */ diff --git a/src/soc/mediatek/mt8192/spi.c b/src/soc/mediatek/mt8192/spi.c index 577536a9f7..d35e5ad3ca 100644 --- a/src/soc/mediatek/mt8192/spi.c +++ b/src/soc/mediatek/mt8192/spi.c @@ -3,6 +3,7 @@ #include <device/mmio.h> #include <assert.h> #include <soc/addressmap.h> +#include <soc/flash_controller.h> #include <soc/gpio.h> #include <soc/spi.h> @@ -128,12 +129,22 @@ void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks, ((cs_ticks - 1) << SPI_CFG1_CS_IDLE_SHIFT)); } +static const struct spi_ctrlr spi_flash_ctrlr = { + .max_xfer_size = 65535, + .flash_probe = mtk_spi_flash_probe, +}; + const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { { .ctrlr = &spi_ctrlr, .bus_start = 0, .bus_end = SPI_BUS_NUMBER - 1, }, + { + .ctrlr = &spi_flash_ctrlr, + .bus_start = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, + .bus_end = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, + }, }; const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); |