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authorMaxim Polyakov <max.senia.poliak@gmail.com>2020-02-26 12:39:09 +0300
committerPatrick Georgi <pgeorgi@google.com>2020-03-06 07:59:29 +0000
commitbb65180ee8b2cb26ac75fe6ccc9525ecc060c1e3 (patch)
tree2b1b751c15a6004b0dfab11eee300139276e0b58
parent3b89ebd8913427b018ca895d7a0683f403029bdf (diff)
downloadcoreboot-bb65180ee8b2cb26ac75fe6ccc9525ecc060c1e3.tar.xz
mb/up/squared: move USB config to device tree
Change-Id: Ic4db37112e7b2329f9e4885139deca12557ffe3a Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39134 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/mainboard/up/squared/devicetree.cb14
-rw-r--r--src/mainboard/up/squared/ramstage.c10
2 files changed, 14 insertions, 10 deletions
diff --git a/src/mainboard/up/squared/devicetree.cb b/src/mainboard/up/squared/devicetree.cb
index 66be75cc05..d7281a6cd8 100644
--- a/src/mainboard/up/squared/devicetree.cb
+++ b/src/mainboard/up/squared/devicetree.cb
@@ -1,5 +1,19 @@
chip soc/intel/apollolake
+ # Override USB port configuration
+ register "usb_config_override" = "1"
+ # USB 2.0
+ register "usb2_port[0]" = "PORT_EN(OC0)"
+ register "usb2_port[1]" = "PORT_EN(OC1)"
+ register "usb2_port[2]" = "PORT_EN(OC1)"
+ register "usb2_port[3]" = "PORT_EN(OC1)"
+ register "usb2_port[4]" = "PORT_EN(OC1)"
+ register "usb2_port[5]" = "PORT_EN(OC1)"
+ register "usb2_port[6]" = "PORT_EN(OC_SKIP)"
+ register "usb2_port[7]" = "PORT_EN(OC_SKIP)"
+ # USB 3.0
+ register "usb3_port[0]" = "PORT_EN(OC0)"
+
register "enable_vtd" = "1"
device cpu_cluster 0 on
diff --git a/src/mainboard/up/squared/ramstage.c b/src/mainboard/up/squared/ramstage.c
index 637b8d87c9..9ae30ebb16 100644
--- a/src/mainboard/up/squared/ramstage.c
+++ b/src/mainboard/up/squared/ramstage.c
@@ -80,14 +80,4 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *silconfig)
silconfig->PcieRpTransmitterHalfSwing[5] = 0x0; // 0x1
silconfig->PcieRpLtrMaxNonSnoopLatency[5] = 0x1003; // 0x0
silconfig->PcieRpLtrMaxSnoopLatency[5] = 0x1003; // 0x0
-
- silconfig->PortUs30bOverCurrentPin[0] = 0x0; // 0x1
-
- silconfig->PortUs20bOverCurrentPin[1] = 0x1; // 0x0
- silconfig->PortUs20bOverCurrentPin[2] = 0x1; // 0x0
- silconfig->PortUs20bOverCurrentPin[3] = 0x1; // 0x0
- silconfig->PortUs20bOverCurrentPin[4] = 0x1; // 0x0
- silconfig->PortUs20bOverCurrentPin[5] = 0x1; // 0x0
- silconfig->PortUs20bOverCurrentPin[6] = 0x2; // 0x0
- silconfig->PortUs20bOverCurrentPin[7] = 0x2; // 0x0
}