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authorMorgan Jang <Morgan_Jang@wiwynn.com>2020-10-07 14:02:49 +0800
committerAngel Pons <th3fanbus@gmail.com>2020-10-28 10:09:32 +0000
commitbdd863689dd2902e2999971b8bf9ea3d811aab8a (patch)
tree819d489e9cecb2b31f7132d3a97035e1b2afa57d
parent160cb331fca8d7a389b25bce30cb3e3cc3a7b4cc (diff)
downloadcoreboot-bdd863689dd2902e2999971b8bf9ea3d811aab8a.tar.xz
src/soc/intel/xeon_sp: Fill in the cache information in SMBIOS type 7
TEST=Execute "dmidecode -t 7" to check if cache error correction type and cache sram type is correct for each cache level Change-Id: Ibe7c6ad03a83a6a3b2c7dfcfafaa619e690a418d Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
-rw-r--r--src/soc/intel/xeon_sp/Makefile.inc2
-rw-r--r--src/soc/intel/xeon_sp/ramstage.c26
2 files changed, 27 insertions, 1 deletions
diff --git a/src/soc/intel/xeon_sp/Makefile.inc b/src/soc/intel/xeon_sp/Makefile.inc
index 8a26c14acc..ffc55b6d4a 100644
--- a/src/soc/intel/xeon_sp/Makefile.inc
+++ b/src/soc/intel/xeon_sp/Makefile.inc
@@ -7,7 +7,7 @@ subdirs-$(CONFIG_SOC_INTEL_COOPERLAKE_SP) += cpx
bootblock-y += bootblock.c spi.c lpc.c gpio.c pch.c
romstage-y += romstage.c reset.c util.c spi.c gpio.c pmutil.c
-ramstage-y += uncore.c reset.c util.c lpc.c spi.c gpio.c nb_acpi.c
+ramstage-y += uncore.c reset.c util.c lpc.c spi.c gpio.c nb_acpi.c ramstage.c
ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmc.c
postcar-y += spi.c
diff --git a/src/soc/intel/xeon_sp/ramstage.c b/src/soc/intel/xeon_sp/ramstage.c
new file mode 100644
index 0000000000..68d5d4658c
--- /dev/null
+++ b/src/soc/intel/xeon_sp/ramstage.c
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <smbios.h>
+
+unsigned int smbios_cache_error_correction_type(u8 level)
+{
+ return SMBIOS_CACHE_ERROR_CORRECTION_SINGLE_BIT;
+}
+
+unsigned int smbios_cache_sram_type(void)
+{
+ return SMBIOS_CACHE_SRAM_TYPE_SYNCHRONOUS;
+}
+
+unsigned int smbios_cache_conf_operation_mode(u8 level)
+{
+ switch (level) {
+ case 1:
+ return SMBIOS_CACHE_OP_MODE_WRITE_BACK;
+ case 2:
+ case 3:
+ return SMBIOS_CACHE_OP_MODE_VARIES_WITH_MEMORY_ADDRESS;
+ default:
+ return SMBIOS_CACHE_OP_MODE_UNKNOWN;
+ }
+}