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authorAaron Durbin <adurbin@chromium.org>2016-08-11 14:51:38 -0500
committerMartin Roth <martinroth@google.com>2016-08-19 18:14:20 +0200
commitc0a823c737d984cd212b2018a71b37fbf9146111 (patch)
tree027c6382bd8bf6b479f2c51488bb0ea3772ea755
parent2e03fbced7551211b801f7d01d5c0b0e7dcad323 (diff)
downloadcoreboot-c0a823c737d984cd212b2018a71b37fbf9146111.tar.xz
drivers/spi: ensure SPI flash is boot device for coreboot tables
The spi_flash_probe() routine was setting a global varible unconditonally regardless if the probe was for the boot device or even if the boot devcie was flash. Moreover, there's no need to report the SPI information if the boot device isn't even SPI. Lastly, it's possible that the boot device is a SPI flash, but the platform may never probe (selecting SPI_FLASH) for the actual device connected. In that situation don't fill anything in as no correct information is known. BUG=chrome-os-partner:56151 Change-Id: Ib0eba601df4d77bede313c358c92b0536355bbd0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16197 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
-rw-r--r--src/drivers/spi/spi_flash.c18
-rw-r--r--src/lib/coreboot_table.c13
2 files changed, 21 insertions, 10 deletions
diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c
index 690b277592..60064208d2 100644
--- a/src/drivers/spi/spi_flash.c
+++ b/src/drivers/spi/spi_flash.c
@@ -11,6 +11,7 @@
#include <cbfs.h>
#include <cpu/x86/smm.h>
#include <delay.h>
+#include <rules.h>
#include <stdlib.h>
#include <string.h>
#include <spi-generic.h>
@@ -372,7 +373,13 @@ flash_detected:
printk(BIOS_INFO, "SF: Detected %s with sector size 0x%x, total 0x%x\n",
flash->name, flash->sector_size, flash->size);
- spi_flash_dev = flash;
+ /*
+ * Only set the global spi_flash_dev if this is the boot
+ * device's bus and it's previously unset while in ramstage.
+ */
+ if (ENV_RAMSTAGE && IS_ENABLED(CONFIG_BOOT_DEVICE_SPI_FLASH) &&
+ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS == bus && !spi_flash_dev)
+ spi_flash_dev = flash;
return flash;
@@ -381,14 +388,13 @@ err_read_id:
return NULL;
}
-/* Only the RAM stage will build in the lb_new_record symbol
- * so only define this function if we are after that stage */
-#ifdef __RAMSTAGE__
-
void lb_spi_flash(struct lb_header *header)
{
struct lb_spi_flash *flash;
+ if (!IS_ENABLED(CONFIG_BOOT_DEVICE_SPI_FLASH))
+ return;
+
flash = (struct lb_spi_flash *)lb_new_record(header);
flash->tag = LB_TAG_SPI_FLASH;
@@ -410,5 +416,3 @@ void lb_spi_flash(struct lb_header *header)
flash->erase_cmd = CMD_BLOCK_ERASE;
}
}
-
-#endif
diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c
index 44ae733e9d..f8da6580cb 100644
--- a/src/lib/coreboot_table.c
+++ b/src/lib/coreboot_table.c
@@ -419,6 +419,14 @@ static void lb_record_version_timestamp(struct lb_header *header)
void __attribute__((weak)) lb_board(struct lb_header *header) { /* NOOP */ }
+/*
+ * It's possible that the system is using a SPI flash as the boot device,
+ * however it is not probing for devices to fill in specifics. In that
+ * case don't provide any information as the correct information is
+ * not known.
+ */
+void __attribute__((weak)) lb_spi_flash(struct lb_header *header) { /* NOOP */ }
+
static struct lb_forward *lb_forward(struct lb_header *header, struct lb_header *next_header)
{
struct lb_record *rec;
@@ -532,10 +540,9 @@ static uintptr_t write_coreboot_table(uintptr_t rom_table_end)
/* Add RAM config if available */
lb_ram_code(head);
-#if IS_ENABLED(CONFIG_SPI_FLASH)
/* Add SPI flash description if available */
- lb_spi_flash(head);
-#endif
+ if (IS_ENABLED(CONFIG_BOOT_DEVICE_SPI_FLASH))
+ lb_spi_flash(head);
add_cbmem_pointers(head);