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authorMario Scheithauer <mario.scheithauer@siemens.com>2018-11-09 08:54:35 +0100
committerWerner Zeh <werner.zeh@siemens.com>2018-11-12 07:26:46 +0000
commitc27ce827dc788e2c34d72fcc43097d8e858e2f9f (patch)
treeed2f9455b209f3bfca16bc4ca39397e2fe9ba379
parent4946804f0b6536df3e7a46654c0dbbc3172b1de8 (diff)
downloadcoreboot-c27ce827dc788e2c34d72fcc43097d8e858e2f9f.tar.xz
siemens/mc_apl4: Disable CLKREQ of PCIe root ports
All PCIe root ports of this mainboard do not have an associated CLKREQ signal. Therefore the ports are marked with "CLKREQ_DISABLED". Change-Id: I834b3b0c77223d81c950e27ccfff8e9aeece2aa4 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
-rw-r--r--src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb11
1 files changed, 6 insertions, 5 deletions
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb
index f3e8a77143..a2a2ba1e8b 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb
@@ -6,11 +6,12 @@ chip soc/intel/apollolake
register "sci_irq" = "SCIS_IRQ10"
- # Disable unused clkreq of PCIe root ports
- register "pcie_rp_clkreq_pin[0]" = "3" # PCIe-PCI-Bridge
- register "pcie_rp_clkreq_pin[1]" = "2" # FPGA
- register "pcie_rp_clkreq_pin[2]" = "0" # MACPHY
- register "pcie_rp_clkreq_pin[3]" = "1" # MACPHY
+ # Disable all clkreq of PCIe root ports as SMARC interface do not
+ # have this pins.
+ register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"