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authorTim Wawrzynczak <twawrzynczak@chromium.org>2020-11-10 11:56:18 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-11-30 08:06:13 +0000
commitc67e3c1a905fea91e8ac0973857ad142b0337a00 (patch)
treeadc5414ce536fe5ac3134b2163f91ae9c1fd8585
parentf1b4a7c9d4e8eb5884efab2d29f49812326f66e2 (diff)
downloadcoreboot-c67e3c1a905fea91e8ac0973857ad142b0337a00.tar.xz
soc/intel/tigerlake: Add some helper macros for accessing TCSS DMA devices
Change-Id: I6289d2049fbbb6bb532be3d9e2355c563ec98d1b Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47410 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
-rw-r--r--src/soc/intel/tigerlake/include/soc/pci_devs.h6
1 files changed, 4 insertions, 2 deletions
diff --git a/src/soc/intel/tigerlake/include/soc/pci_devs.h b/src/soc/intel/tigerlake/include/soc/pci_devs.h
index cfb70cdb9f..ac0498fe26 100644
--- a/src/soc/intel/tigerlake/include/soc/pci_devs.h
+++ b/src/soc/intel/tigerlake/include/soc/pci_devs.h
@@ -50,10 +50,12 @@
#define SA_DEV_TBT3 PCI_DEV(0, SA_DEV_SLOT_TBT, 3)
#define SA_DEV_SLOT_TCSS 0x0d
+#define NUM_TCSS_DMA_FUNCTIONS 2
+#define SA_DEVFN_TCSS_DMA(x) PCI_DEVFN(SA_DEV_SLOT_TCSS, ((x) + 2))
#define SA_DEVFN_TCSS_XHCI PCI_DEVFN(SA_DEV_SLOT_TCSS, 0)
#define SA_DEVFN_TCSS_XDCI PCI_DEVFN(SA_DEV_SLOT_TCSS, 1)
-#define SA_DEVFN_TCSS_DMA0 PCI_DEVFN(SA_DEV_SLOT_TCSS, 2)
-#define SA_DEVFN_TCSS_DMA1 PCI_DEVFN(SA_DEV_SLOT_TCSS, 3)
+#define SA_DEVFN_TCSS_DMA0 SA_DEVFN_TCSS_DMA(0)
+#define SA_DEVFN_TCSS_DMA1 SA_DEVFN_TCSS_DMA(1)
#define SA_DEV_TCSS_XHCI PCI_DEV(0, SA_DEV_SLOT_TCSS, 0)
#define SA_DEV_TCSS_XDCI PCI_DEV(0, SA_DEV_SLOT_TCSS, 1)
#define SA_DEV_TCSS_DMA0 PCI_DEV(0, SA_DEV_SLOT_TCSS, 2)