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authorAaron Durbin <adurbin@chromium.org>2013-03-22 22:03:09 -0500
committerStefan Reinauer <stefan.reinauer@coreboot.org>2013-03-23 19:40:36 +0100
commitc965076c3ecec6ccf8eb0eb1d57d6a0a312dab04 (patch)
tree6f5238941a7dd03c66a665025cc414156484667b
parent0135702802601c19937eec57513f3a6e2f4d1e00 (diff)
downloadcoreboot-c965076c3ecec6ccf8eb0eb1d57d6a0a312dab04.tar.xz
resources: introduce reserved_ram_resource()
mmio_resource() was previously being used for reserving RAM from the OS by using IORESOURCE_IGNORE_MTRR atrribute. Instead, be more explicit for those uses with reserved_ram_resource(). bad_ram_resource() now calls reserved_ram_resource(). Those resources are marked as cacheable but reserved. The sandybridge and haswell code were relying on the implementation fo the MTRR algorithm's interaction for reserved regions. Instead be explicit about what ranges are MMIO reserved and what are RAM reserved. Change-Id: I1e47026970fb37c0305e4d49a12c98b0cdd1abe5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2886 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
-rw-r--r--src/include/device/device.h5
-rw-r--r--src/northbridge/intel/haswell/northbridge.c21
-rw-r--r--src/northbridge/intel/sandybridge/northbridge.c8
3 files changed, 20 insertions, 14 deletions
diff --git a/src/include/device/device.h b/src/include/device/device.h
index 5219310202..b8dfbf51cf 100644
--- a/src/include/device/device.h
+++ b/src/include/device/device.h
@@ -206,8 +206,11 @@ void fixed_mem_resource(device_t dev, unsigned long index,
#define ram_resource(dev, idx, basek, sizek) \
fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_CACHEABLE)
+#define reserved_ram_resource(dev, idx, basek, sizek) \
+ fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_CACHEABLE | IORESOURCE_RESERVE | IORESOURCE_IGNORE_MTRR)
+
#define bad_ram_resource(dev, idx, basek, sizek) \
- fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_RESERVE | IORESOURCE_IGNORE_MTRR)
+ reserved_ram_resource((dev), (idx), (basek), (sizek))
#define uma_resource(dev, idx, basek, sizek) \
fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_RESERVE | IORESOURCE_UMA_FB)
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c
index b57b28e632..16196ad6ad 100644
--- a/src/northbridge/intel/haswell/northbridge.c
+++ b/src/northbridge/intel/haswell/northbridge.c
@@ -53,15 +53,6 @@ int bridge_silicon_revision(void)
return bridge_revision_id;
}
-/* Reserve everything between A segment and 1MB:
- *
- * 0xa0000 - 0xbffff: legacy VGA
- * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel)
- * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI
- */
-static const int legacy_hole_base_k = 0xa0000 / 1024;
-static const int legacy_hole_size_k = 384;
-
void cbmem_post_handling(void)
{
update_mrc_cache();
@@ -414,9 +405,17 @@ static void mc_add_dram_resources(device_t dev)
if (size_k > 0)
ram_resource(dev, index++, base_k, size_k);
- mmio_resource(dev, index++, legacy_hole_base_k, legacy_hole_size_k);
+ /* Reserve everything between A segment and 1MB:
+ *
+ * 0xa0000 - 0xbffff: legacy VGA
+ * 0xc0000 - 0xfffff: RAM
+ */
+ mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10);
+ reserved_ram_resource(dev, index++, (0xc0000 >> 10),
+ (0x100000 - 0xc0000) >> 10);
#if CONFIG_CHROMEOS_RAMOOPS
- mmio_resource(dev, index++, CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10,
+ reserved_ram_resource(dev, index++,
+ CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10,
CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10);
#endif
}
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index 13390bdfa9..c39933f1c1 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -127,10 +127,14 @@ static void add_fixed_resources(struct device *dev, int index)
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
}
- mmio_resource(dev, index++, legacy_hole_base_k, legacy_hole_size_k);
+ mmio_resource(dev, index++, legacy_hole_base_k,
+ (0xc0000 >> 10) - legacy_hole_base_k);
+ reserved_ram_resource(dev, index++, 0xc0000 >> 10,
+ (0x100000 - 0xc0000) >> 10);
#if CONFIG_CHROMEOS_RAMOOPS
- mmio_resource(dev, index++, CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10,
+ reserved_ram_resource(dev, index++,
+ CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10,
CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10);
#endif