mb/ocp/tiogapass: Configure IPMI FRB2 watchdog timer via VPD variables

Add VPD variables for enabling/disabling FRB2 watchdog timer and setting
the timer countdown value in romstage. By default it would start the timer
and trigger hard reset when it's expired. The timer is expected to be
stopped later by payload or OS.

Add RO_VPD and RW_VPD sections.

Tested on OCP Tioga Pass.

Change-Id: I53b69c3c5d22c022130fd812ef26097898d913d0
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

7 files changed, 67 insertions, 2 deletions

diff --git a/src/mainboard/ocp/tiogapass/Kconfig b/src/mainboard/ocp/tiogapass/Kconfig
index 79dafa7845..67c1fa9d52 100644
--- a/src/mainboard/ocp/tiogapass/Kconfig
+++ b/src/mainboard/ocp/tiogapass/Kconfig
@@ -7,11 +7,13 @@ config BOARD_SPECIFIC_OPTIONS
 	select BOARD_ROMSIZE_KB_32768
 	select HAVE_ACPI_TABLES
 	select IPMI_KCS
+	select IPMI_KCS_ROMSTAGE
 	select MAINBOARD_USES_FSP2_0
 	select OCP_DMI
 	select PARALLEL_MP_AP_WORK
 	select SOC_INTEL_SKYLAKE_SP
 	select SUPERIO_ASPEED_AST2400
+	select VPD
 
 config MAINBOARD_DIR
 	string
diff --git a/src/mainboard/ocp/tiogapass/Makefile.inc b/src/mainboard/ocp/tiogapass/Makefile.inc
index bb4a86beb3..2f7f327960 100644
--- a/src/mainboard/ocp/tiogapass/Makefile.inc
+++ b/src/mainboard/ocp/tiogapass/Makefile.inc
@@ -1,6 +1,7 @@
 ## SPDX-License-Identifier: GPL-2.0-or-later
 
 bootblock-y += bootblock.c
+romstage-y += ipmi.c
 ramstage-y += ramstage.c ipmi.c
 
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
diff --git a/src/mainboard/ocp/tiogapass/board.fmd b/src/mainboard/ocp/tiogapass/board.fmd
index 1e3fda7e8b..2ecce06570 100644
--- a/src/mainboard/ocp/tiogapass/board.fmd
+++ b/src/mainboard/ocp/tiogapass/board.fmd
@@ -5,7 +5,15 @@ FLASH 32M {
 		PLATFORM_DATA@0xa26000 0x10000
 	}
 	SI_BIOS@0x1000000 0x1000000 {
-		FMAP@0x0 0x800
-		COREBOOT(CBFS)@0x800 0xfff800
+		MISC_RW@0x0 0x10000 {
+			RW_VPD(PRESERVE)@0x0 0x4000
+		}
+		WP_RO@0x10000 0xff0000 {
+			RO_VPD(PRESERVE)@0x0 0x4000
+			RO_SECTION@0x4000 0xfec000 {
+				FMAP@0x0 0x800
+				COREBOOT(CBFS)@0x800 0xfeb800
+			}
+		}
 	}
 }
diff --git a/src/mainboard/ocp/tiogapass/ipmi.c b/src/mainboard/ocp/tiogapass/ipmi.c
index aa50688db5..0cdf110bd8 100644
--- a/src/mainboard/ocp/tiogapass/ipmi.c
+++ b/src/mainboard/ocp/tiogapass/ipmi.c
@@ -2,8 +2,12 @@
 
 #include <console/console.h>
 #include <drivers/ipmi/ipmi_kcs.h>
+#include <drivers/ipmi/ipmi_ops.h>
+#include <drivers/vpd/vpd.h>
+#include <string.h>
 
 #include "ipmi.h"
+#include "vpd.h"
 
 void ipmi_set_ppin(struct ppin_req *req)
 {
@@ -21,3 +25,32 @@ void ipmi_set_ppin(struct ppin_req *req)
 	}
 	printk(BIOS_DEBUG, "IPMI Set PPIN to BMC done.\n");
 }
+
+void init_frb2_wdt(void)
+{
+	char val[VPD_LEN];
+	/* Enable FRB2 timer by default. */
+	u8 enable = 1;
+	uint16_t countdown;
+
+	if (vpd_get_bool(FRB2_TIMER, VPD_RW_THEN_RO, &enable)) {
+		if (!enable) {
+			printk(BIOS_DEBUG, "Disable FRB2 timer\n");
+			ipmi_stop_bmc_wdt(CONFIG_BMC_KCS_BASE);
+			return;
+		}
+	}
+	if (enable) {
+		if (vpd_gets(FRB2_COUNTDOWN, val, VPD_LEN, VPD_RW_THEN_RO)) {
+			countdown = (uint16_t)atol(val);
+			printk(BIOS_DEBUG, "FRB2 timer countdown set to: %d ms\n",
+				countdown * 100);
+		} else {
+			printk(BIOS_DEBUG, "FRB2 timer use default value: %d ms\n",
+				DEFAULT_COUNTDOWN * 100);
+			countdown = DEFAULT_COUNTDOWN;
+		}
+		ipmi_init_and_start_bmc_wdt(CONFIG_BMC_KCS_BASE, countdown,
+			TIMEOUT_HARD_RESET);
+	}
+}
diff --git a/src/mainboard/ocp/tiogapass/ipmi.h b/src/mainboard/ocp/tiogapass/ipmi.h
index 3d2723f49e..798f3125ef 100644
--- a/src/mainboard/ocp/tiogapass/ipmi.h
+++ b/src/mainboard/ocp/tiogapass/ipmi.h
@@ -16,4 +16,5 @@ struct ppin_req {
 } __packed;
 /* Send CPU0 and CPU1 PPIN to BMC */
 void ipmi_set_ppin(struct ppin_req *req);
+void init_frb2_wdt(void);
 #endif
diff --git a/src/mainboard/ocp/tiogapass/romstage.c b/src/mainboard/ocp/tiogapass/romstage.c
index b728c3a5c5..fb2ce0217a 100644
--- a/src/mainboard/ocp/tiogapass/romstage.c
+++ b/src/mainboard/ocp/tiogapass/romstage.c
@@ -2,12 +2,15 @@
 
 #include <fsp/api.h>
 #include <FspmUpd.h>
+#include <drivers/ipmi/ipmi_kcs.h>
 #include <soc/romstage.h>
 #include <string.h>
 #include <gpio.h>
 #include <soc/lewisburg_pch_gpio_defs.h>
 #include <skxsp_tp_iio.h>
 
+#include "ipmi.h"
+
 static uint8_t iio_table_buf[sizeof(tp_iio_bifur_table)];
 
 static void oem_update_iio(FSPM_UPD *mupd)
@@ -49,6 +52,9 @@ static void mainboard_config_iio(FSPM_UPD *mupd)
 
 void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
+	/* It's better to run get BMC selftest result first */
+	if (ipmi_kcs_premem_init(CONFIG_BMC_KCS_BASE, 0) == CB_SUCCESS)
+		init_frb2_wdt();
 	mainboard_config_iio(mupd);
 
 	/* do not configure GPIO controller inside FSP-M */
diff --git a/src/mainboard/ocp/tiogapass/vpd.h b/src/mainboard/ocp/tiogapass/vpd.h
new file mode 100644
index 0000000000..63a92f68b2
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/vpd.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef TIOGAPASS_VPD_H
+#define TIOGAPASS_VPD_H
+
+/* VPD variable for enabling/disabling FRB2 timer. */
+#define FRB2_TIMER "frb2_timer"
+/* VPD variable for setting FRB2 timer countdown value. */
+#define FRB2_COUNTDOWN "frb2_countdown"
+#define VPD_LEN 10
+/* Default countdown is 15 minutes. */
+#define DEFAULT_COUNTDOWN 9000
+
+#endif /* TIOGAPASS_VPD_H */