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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2014-07-22 18:28:21 +0200 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2014-07-24 12:42:44 +0200 |
| commit | e062baacbb1a7c2a824e2894f857af68a03f516f (patch) | |
| tree | 86f98e0ad59e0fd753ffb2d6127b2ff70018843c | |
| parent | e6f43d2e412f23dddb5943393332056be4167e19 (diff) | |
| download | coreboot-e062baacbb1a7c2a824e2894f857af68a03f516f.tar.xz | |
northbridge/via: Remove a trailing whitespace
Change-Id: I959f2d42bb3b6cd37a7876ad4dae712bdb5a69da
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: http://review.coreboot.org/6315
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
| -rw-r--r-- | src/northbridge/via/vx800/dram_init.h | 38 | ||||
| -rw-r--r-- | src/northbridge/via/vx800/driving_clk_phase_data.h | 2 | ||||
| -rw-r--r-- | src/northbridge/via/vx800/vx800.h | 2 |
3 files changed, 21 insertions, 21 deletions
diff --git a/src/northbridge/via/vx800/dram_init.h b/src/northbridge/via/vx800/dram_init.h index c1cb9fb163..3f4fb4a7ee 100644 --- a/src/northbridge/via/vx800/dram_init.h +++ b/src/northbridge/via/vx800/dram_init.h @@ -32,8 +32,8 @@ // UMA size #define UMASIZE M64 -#define ENABLE_CHC 0 //CHC enable, how ever, this CHC,used some reg define in CHB -#define ENABLE_CHB 0 //CHB enable , CHB is VX800's, VX855 no this CHB. +#define ENABLE_CHC 0 //CHC enable, how ever, this CHC,used some reg define in CHB +#define ENABLE_CHB 0 //CHB enable , CHB is VX800's, VX855 no this CHB. //Dram Freq #define DIMMFREQ_800 400 #define DIMMFREQ_667 333 @@ -45,14 +45,14 @@ #define DIMMFREQ_200 100 //Dram Type -#define RAMTYPE_FPMDRAM 1 -#define RAMTYPE_EDO 2 -#define RAMTYPE_PipelinedNibble 3 -#define RAMTYPE_SDRAM 4 -#define RAMTYPE_ROM 5 -#define RAMTYPE_SGRAMDDR 6 -#define RAMTYPE_SDRAMDDR 7 -#define RAMTYPE_SDRAMDDR2 8 +#define RAMTYPE_FPMDRAM 1 +#define RAMTYPE_EDO 2 +#define RAMTYPE_PipelinedNibble 3 +#define RAMTYPE_SDRAM 4 +#define RAMTYPE_ROM 5 +#define RAMTYPE_SGRAMDDR 6 +#define RAMTYPE_SDRAMDDR 7 +#define RAMTYPE_SDRAMDDR2 8 /* CAS latency constant */ #define CASLAN_15 15 @@ -66,13 +66,13 @@ #define CASLAN_NULL 00 //Burst length -#define BURSTLENGTH8 8 -#define BURSTLENGTH4 4 +#define BURSTLENGTH8 8 +#define BURSTLENGTH4 4 //Data Width -//#define DATAWIDTHX16 16 -//#define DATAWIDTHX8 8 -//#define DATAWIDTHX4 4 +//#define DATAWIDTHX16 16 +//#define DATAWIDTHX8 8 +//#define DATAWIDTHX4 4 #define SPD_MEMORY_TYPE 2 /*Memory type FPM,EDO,SDRAM,DDR,DDR2 */ #define SPD_SDRAM_ROW_ADDR 3 /*Number of row addresses on this assembly */ @@ -107,15 +107,15 @@ #define SPC_SDRAM_TRC 41 /*minimum active to active/refresh time */ #define SPD_SDRAM_TRFC 42 /*minimum refresh to active / refresh command period */ -#define SPD_DATA_SIZE 44 +#define SPD_DATA_SIZE 44 //Dram cofig are /*the most number of socket*/ -#define MAX_RAM_SLOTS 2 +#define MAX_RAM_SLOTS 2 #define MAX_SOCKETS MAX_RAM_SLOTS -#define MAX_DIMMS MAX_SOCKETS /*every sockets can plug one DIMM */ +#define MAX_DIMMS MAX_SOCKETS /*every sockets can plug one DIMM */ /*the most number of RANKs on a DIMM*/ -#define MAX_RANKS MAX_SOCKETS*2 +#define MAX_RANKS MAX_SOCKETS*2 struct mem_controller { u8 channel0[MAX_DIMMS]; diff --git a/src/northbridge/via/vx800/driving_clk_phase_data.h b/src/northbridge/via/vx800/driving_clk_phase_data.h index ebc82bed1b..c211e1a0d1 100644 --- a/src/northbridge/via/vx800/driving_clk_phase_data.h +++ b/src/northbridge/via/vx800/driving_clk_phase_data.h @@ -31,7 +31,7 @@ //extern u8 DDR2_CSA_Driving_Table_x16[4]; //extern u8 DDR2_CSB_Driving_Table_x16[2]; -#define MA_Table 3 +#define MA_Table 3 //extern u8 DDR2_MAA_Driving_Table[MA_Table][4]; //extern u8 DDR2_MAB_Driving_Table[MA_Table][2]; diff --git a/src/northbridge/via/vx800/vx800.h b/src/northbridge/via/vx800/vx800.h index ce1f0a16ec..adfe27209a 100644 --- a/src/northbridge/via/vx800/vx800.h +++ b/src/northbridge/via/vx800/vx800.h @@ -18,7 +18,7 @@ */ #ifndef VX800_H -#define VX800_H 1 +#define VX800_H 1 #ifndef __PRE_RAM__ #include <device/device.h> |