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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-10 17:27:01 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-13 13:59:05 +0000
commite31ec299decd5a07e14fbd680eb88d34561c646d (patch)
treed0c0708fb5194ce7bdbae6345387533d1883bfba
parent08456363f2e30980fa40556bea1c8b0d7e69f7ec (diff)
downloadcoreboot-e31ec299decd5a07e14fbd680eb88d34561c646d.tar.xz
cpu/x86: Separate save_state struct headers
Any platform should need just one of these. Change-Id: Ia0ff8eff152cbd3d82e8b372ec662d3737078d35 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34820 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/cpu/intel/haswell/smmrelocate.c1
-rw-r--r--src/cpu/intel/smm/gen1/smmrelocate.c1
-rw-r--r--src/cpu/x86/smm/smihandler.c1
-rw-r--r--src/include/cpu/amd/amd64_save_state.h124
-rw-r--r--src/include/cpu/intel/em64t100_save_state.h106
-rw-r--r--src/include/cpu/intel/em64t101_save_state.h120
-rw-r--r--src/include/cpu/intel/em64t_save_state.h101
-rw-r--r--src/include/cpu/x86/legacy_save_state.h59
-rw-r--r--src/include/cpu/x86/smi_deprecated.h46
-rw-r--r--src/include/cpu/x86/smm.h445
-rw-r--r--src/soc/amd/picasso/cpu.c1
-rw-r--r--src/soc/amd/picasso/smihandler.c1
-rw-r--r--src/soc/amd/stoneyridge/cpu.c1
-rw-r--r--src/soc/amd/stoneyridge/smihandler.c1
-rw-r--r--src/soc/intel/apollolake/cpu.c1
-rw-r--r--src/soc/intel/apollolake/smihandler.c1
-rw-r--r--src/soc/intel/baytrail/cpu.c1
-rw-r--r--src/soc/intel/baytrail/smihandler.c1
-rw-r--r--src/soc/intel/braswell/cpu.c1
-rw-r--r--src/soc/intel/braswell/smihandler.c1
-rw-r--r--src/soc/intel/broadwell/smihandler.c1
-rw-r--r--src/soc/intel/broadwell/smmrelocate.c1
-rw-r--r--src/soc/intel/cannonlake/smmrelocate.c1
-rw-r--r--src/soc/intel/common/block/smm/smihandler.c2
-rw-r--r--src/soc/intel/denverton_ns/cpu.c1
-rw-r--r--src/soc/intel/denverton_ns/smihandler.c1
-rw-r--r--src/soc/intel/fsp_baytrail/cpu.c1
-rw-r--r--src/soc/intel/fsp_baytrail/smihandler.c1
-rw-r--r--src/soc/intel/fsp_broadwell_de/smmrelocate.c1
-rw-r--r--src/soc/intel/icelake/smmrelocate.c1
-rw-r--r--src/soc/intel/skylake/smmrelocate.c1
-rw-r--r--src/southbridge/amd/agesa/hudson/smihandler.c1
-rw-r--r--src/southbridge/amd/pi/hudson/smihandler.c1
-rw-r--r--src/southbridge/intel/bd82x6x/smihandler.c1
-rw-r--r--src/southbridge/intel/common/pmutil.h1
-rw-r--r--src/southbridge/intel/common/smihandler.c2
-rw-r--r--src/southbridge/intel/i82801dx/smihandler.c1
-rw-r--r--src/southbridge/intel/ibexpeak/smihandler.c1
-rw-r--r--src/southbridge/intel/lynxpoint/smihandler.c1
39 files changed, 592 insertions, 443 deletions
diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c
index 3a4a0a7830..f3e0cbf240 100644
--- a/src/cpu/intel/haswell/smmrelocate.c
+++ b/src/cpu/intel/haswell/smmrelocate.c
@@ -24,6 +24,7 @@
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h>
+#include <cpu/intel/em64t101_save_state.h>
#include <console/console.h>
#include <northbridge/intel/haswell/haswell.h>
#include <southbridge/intel/lynxpoint/pch.h>
diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c
index d8021e6ac2..fd98c3057c 100644
--- a/src/cpu/intel/smm/gen1/smmrelocate.c
+++ b/src/cpu/intel/smm/gen1/smmrelocate.c
@@ -27,6 +27,7 @@
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h>
+#include <cpu/intel/em64t101_save_state.h>
#include <console/console.h>
#include <smp/node.h>
#include "smi.h"
diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c
index bc01522291..e4b1d6a622 100644
--- a/src/cpu/x86/smm/smihandler.c
+++ b/src/cpu/x86/smm/smihandler.c
@@ -18,6 +18,7 @@
#include <console/console.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/smm.h>
+#include <cpu/x86/smi_deprecated.h>
#if CONFIG(SPI_FLASH_SMM)
#include <spi-generic.h>
diff --git a/src/include/cpu/amd/amd64_save_state.h b/src/include/cpu/amd/amd64_save_state.h
new file mode 100644
index 0000000000..14149ece37
--- /dev/null
+++ b/src/include/cpu/amd/amd64_save_state.h
@@ -0,0 +1,124 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __AMD64_SAVE_STATE_H__
+#define __AMD64_SAVE_STATE_H__
+#endif
+
+#include <types.h>
+#include <cpu/x86/smm.h>
+
+/* AMD64 x86 SMM State-Save Area
+ * starts @ 0x7e00
+ */
+#define SMM_AMD64_ARCH_OFFSET 0x7e00
+#define SMM_AMD64_SAVE_STATE_OFFSET \
+ SMM_SAVE_STATE_BEGIN(SMM_AMD64_ARCH_OFFSET)
+typedef struct {
+ u16 es_selector;
+ u16 es_attributes;
+ u32 es_limit;
+ u64 es_base;
+
+ u16 cs_selector;
+ u16 cs_attributcs;
+ u32 cs_limit;
+ u64 cs_base;
+
+ u16 ss_selector;
+ u16 ss_attributss;
+ u32 ss_limit;
+ u64 ss_base;
+
+ u16 ds_selector;
+ u16 ds_attributds;
+ u32 ds_limit;
+ u64 ds_base;
+
+ u16 fs_selector;
+ u16 fs_attributfs;
+ u32 fs_limit;
+ u64 fs_base;
+
+ u16 gs_selector;
+ u16 gs_attributgs;
+ u32 gs_limit;
+ u64 gs_base;
+
+ u8 reserved0[4];
+ u16 gdtr_limit;
+ u8 reserved1[2];
+ u64 gdtr_base;
+
+ u16 ldtr_selector;
+ u16 ldtr_attributes;
+ u32 ldtr_limit;
+ u64 ldtr_base;
+
+ u8 reserved2[4];
+ u16 idtr_limit;
+ u8 reserved3[2];
+ u64 idtr_base;
+
+ u16 tr_selector;
+ u16 tr_attributes;
+ u32 tr_limit;
+ u64 tr_base;
+
+ u64 io_restart_rip;
+ u64 io_restart_rcx;
+ u64 io_restart_rsi;
+ u64 io_restart_rdi;
+ u32 smm_io_trap_offset;
+ u32 local_smi_status;
+
+ u8 io_restart;
+ u8 autohalt_restart;
+
+ u8 reserved5[6];
+
+ u64 efer;
+
+ u8 reserved6[36];
+
+ u32 smm_revision;
+ u32 smbase;
+
+ u8 reserved7[68];
+
+ u64 cr4;
+ u64 cr3;
+ u64 cr0;
+ u64 dr7;
+ u64 dr6;
+
+ u64 rflags;
+ u64 rip;
+ u64 r15;
+ u64 r14;
+ u64 r13;
+ u64 r12;
+ u64 r11;
+ u64 r10;
+ u64 r9;
+ u64 r8;
+
+ u64 rdi;
+ u64 rsi;
+ u64 rpb;
+ u64 rsp;
+ u64 rbx;
+ u64 rdx;
+ u64 rcx;
+ u64 rax;
+} __packed amd64_smm_state_save_area_t;
diff --git a/src/include/cpu/intel/em64t100_save_state.h b/src/include/cpu/intel/em64t100_save_state.h
new file mode 100644
index 0000000000..f76fa4badd
--- /dev/null
+++ b/src/include/cpu/intel/em64t100_save_state.h
@@ -0,0 +1,106 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __EM64T100_SAVE_STATE_H__
+#define __EM64T100_SAVE_STATE_H__
+
+#include <types.h>
+#include <cpu/x86/smm.h>
+
+/* Intel Revision 30100 SMM State-Save Area
+ * The following processor architectures use this:
+ * - Bay Trail
+ */
+#define SMM_EM64T100_ARCH_OFFSET 0x7c00
+#define SMM_EM64T100_SAVE_STATE_OFFSET \
+ SMM_SAVE_STATE_BEGIN(SMM_EM64T100_ARCH_OFFSET)
+typedef struct {
+ u8 reserved0[256];
+ u8 reserved1[208];
+
+ u32 gdtr_upper_base;
+ u32 ldtr_upper_base;
+ u32 idtr_upper_base;
+
+ u8 reserved2[4];
+
+ u64 io_rdi;
+ u64 io_rip;
+ u64 io_rcx;
+ u64 io_rsi;
+
+ u8 reserved3[64];
+ u32 cr4;
+
+ u8 reserved4[72];
+
+ u32 gdtr_base;
+ u8 reserved5[4];
+ u32 idtr_base;
+ u8 reserved6[4];
+ u32 ldtr_base;
+
+ u8 reserved7[88];
+
+ u32 smbase;
+ u32 smm_revision;
+
+ u16 io_restart;
+ u16 autohalt_restart;
+
+ u8 reserved8[24];
+
+ u64 r15;
+ u64 r14;
+ u64 r13;
+ u64 r12;
+ u64 r11;
+ u64 r10;
+ u64 r9;
+ u64 r8;
+
+ u64 rax;
+ u64 rcx;
+ u64 rdx;
+ u64 rbx;
+
+ u64 rsp;
+ u64 rbp;
+ u64 rsi;
+ u64 rdi;
+
+
+ u64 io_mem_addr;
+ u32 io_misc_info;
+
+ u32 es_sel;
+ u32 cs_sel;
+ u32 ss_sel;
+ u32 ds_sel;
+ u32 fs_sel;
+ u32 gs_sel;
+
+ u32 ldtr_sel;
+ u32 tr_sel;
+
+ u64 dr7;
+ u64 dr6;
+ u64 rip;
+ u64 efer;
+ u64 rflags;
+
+ u64 cr3;
+ u64 cr0;
+} __packed em64t100_smm_state_save_area_t;
+
+#endif
diff --git a/src/include/cpu/intel/em64t101_save_state.h b/src/include/cpu/intel/em64t101_save_state.h
new file mode 100644
index 0000000000..b8bb2db58f
--- /dev/null
+++ b/src/include/cpu/intel/em64t101_save_state.h
@@ -0,0 +1,120 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __EM64T101_SAVE_STATE_H__
+#define __EM64T101_SAVE_STATE_H__
+
+#include <types.h>
+#include <cpu/x86/smm.h>
+
+
+/* Intel Revision 30101 SMM State-Save Area
+ * The following processor architectures use this:
+ * - SandyBridge
+ * - IvyBridge
+ * - Haswell
+ */
+#define SMM_EM64T101_ARCH_OFFSET 0x7c00
+#define SMM_EM64T101_SAVE_STATE_OFFSET \
+ SMM_SAVE_STATE_BEGIN(SMM_EM64T101_ARCH_OFFSET)
+typedef struct {
+ u8 reserved0[256];
+ u8 reserved1[208];
+
+ u32 gdtr_upper_base;
+ u32 ldtr_upper_base;
+ u32 idtr_upper_base;
+
+ u32 io_cf8;
+
+ u64 io_rdi;
+ u64 io_rip;
+ u64 io_rcx;
+ u64 io_rsi;
+
+ u8 reserved2[52];
+ u32 shutdown_auto_restart;
+ u8 reserved3[8];
+ u32 cr4;
+
+ u8 reserved4[72];
+
+ u32 gdtr_base;
+ u8 reserved5[4];
+ u32 idtr_base;
+ u8 reserved6[4];
+ u32 ldtr_base;
+
+ u8 reserved7[56];
+ /* EPTP fields are only on Haswell according to BWGs, but Intel was
+ * wise and reused the same revision number. */
+ u64 eptp;
+ u32 eptp_en;
+ u32 cs_base;
+ u8 reserved8[4];
+ u32 iedbase;
+
+ u8 reserved9[8];
+
+ u32 smbase;
+ u32 smm_revision;
+
+ u16 io_restart;
+ u16 autohalt_restart;
+
+ u8 reserved10[24];
+
+ u64 r15;
+ u64 r14;
+ u64 r13;
+ u64 r12;
+ u64 r11;
+ u64 r10;
+ u64 r9;
+ u64 r8;
+
+ u64 rax;
+ u64 rcx;
+ u64 rdx;
+ u64 rbx;
+
+ u64 rsp;
+ u64 rbp;
+ u64 rsi;
+ u64 rdi;
+
+
+ u64 io_mem_addr;
+ u32 io_misc_info;
+
+ u32 es_sel;
+ u32 cs_sel;
+ u32 ss_sel;
+ u32 ds_sel;
+ u32 fs_sel;
+ u32 gs_sel;
+
+ u32 ldtr_sel;
+ u32 tr_sel;
+
+ u64 dr7;
+ u64 dr6;
+ u64 rip;
+ u64 efer;
+ u64 rflags;
+
+ u64 cr3;
+ u64 cr0;
+} __packed em64t101_smm_state_save_area_t;
+
+#endif
diff --git a/src/include/cpu/intel/em64t_save_state.h b/src/include/cpu/intel/em64t_save_state.h
new file mode 100644
index 0000000000..1dd01a61a4
--- /dev/null
+++ b/src/include/cpu/intel/em64t_save_state.h
@@ -0,0 +1,101 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __EM64T_SAVE_STATE_H__
+#define __EM64T_SAVE_STATE_H__
+
+#include <types.h>
+#include <cpu/x86/smm.h>
+
+/* Intel Core 2 (EM64T) SMM State-Save Area
+ * starts @ 0x7c00
+ */
+#define SMM_EM64T_ARCH_OFFSET 0x7c00
+#define SMM_EM64T_SAVE_STATE_OFFSET \
+ SMM_SAVE_STATE_BEGIN(SMM_EM64T_ARCH_OFFSET)
+typedef struct {
+ u8 reserved0[256];
+ u8 reserved1[208];
+
+ u32 gdtr_upper_base;
+ u32 ldtr_upper_base;
+ u32 idtr_upper_base;
+
+ u8 reserved2[4];
+
+ u64 io_rdi;
+ u64 io_rip;
+ u64 io_rcx;
+ u64 io_rsi;
+ u64 cr4;
+
+ u8 reserved3[68];
+
+ u64 gdtr_base;
+ u64 idtr_base;
+ u64 ldtr_base;
+
+ u8 reserved4[84];
+
+ u32 smm_revision;
+ u32 smbase;
+
+ u16 io_restart;
+ u16 autohalt_restart;
+
+ u8 reserved5[24];
+
+ u64 r15;
+ u64 r14;
+ u64 r13;
+ u64 r12;
+ u64 r11;
+ u64 r10;
+ u64 r9;
+ u64 r8;
+
+ u64 rax;
+ u64 rcx;
+ u64 rdx;
+ u64 rbx;
+
+ u64 rsp;
+ u64 rbp;
+ u64 rsi;
+ u64 rdi;
+
+
+ u64 io_mem_addr;
+ u32 io_misc_info;
+
+ u32 es_sel;
+ u32 cs_sel;
+ u32 ss_sel;
+ u32 ds_sel;
+ u32 fs_sel;
+ u32 gs_sel;
+
+ u32 ldtr_sel;
+ u32 tr_sel;
+
+ u64 dr7;
+ u64 dr6;
+ u64 rip;
+ u64 efer;
+ u64 rflags;
+
+ u64 cr3;
+ u64 cr0;
+} __packed em64t_smm_state_save_area_t;
+
+#endif
diff --git a/src/include/cpu/x86/legacy_save_state.h b/src/include/cpu/x86/legacy_save_state.h
new file mode 100644
index 0000000000..7803db77de
--- /dev/null
+++ b/src/include/cpu/x86/legacy_save_state.h
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __X86_LEGACY_SAVE_STATE_H__
+#define __X86_LEGACY_SAVE_STATE_H__
+
+#include <types.h>
+
+/* Legacy x86 SMM State-Save Area
+ * starts @ 0x7e00
+ */
+#define SMM_LEGACY_ARCH_OFFSET 0x7e00
+
+typedef struct {
+ u8 reserved0[248];
+ u32 smbase;
+ u32 smm_revision;
+ u16 io_restart;
+ u16 autohalt_restart;
+ u8 reserved1[132];
+ u32 gdtbase;
+ u8 reserved2[8];
+ u32 idtbase;
+ u8 reserved3[16];
+ u32 es;
+ u32 cs;
+ u32 ss;
+ u32 ds;
+ u32 fs;
+ u32 gs;
+ u32 ldtbase;
+ u32 tr;
+ u32 dr7;
+ u32 dr6;
+ u32 eax;
+ u32 ecx;
+ u32 edx;
+ u32 ebx;
+ u32 esp;
+ u32 ebp;
+ u32 esi;
+ u32 edi;
+ u32 eip;
+ u32 eflags;
+ u32 cr3;
+ u32 cr0;
+} __packed legacy_smm_state_save_area_t;
+
+#endif
diff --git a/src/include/cpu/x86/smi_deprecated.h b/src/include/cpu/x86/smi_deprecated.h
new file mode 100644
index 0000000000..3eed0fdda5
--- /dev/null
+++ b/src/include/cpu/x86/smi_deprecated.h
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __X86_SMI_DEPRECATED_H__
+#define __X86_SMI_DEPRECATED_H__
+
+#include <cpu/amd/amd64_save_state.h>
+#include <cpu/intel/em64t_save_state.h>
+#include <cpu/intel/em64t100_save_state.h>
+#include <cpu/intel/em64t101_save_state.h>
+#include <cpu/x86/legacy_save_state.h>
+
+typedef enum {
+ AMD64,
+ EM64T,
+ EM64T101,
+ LEGACY
+} save_state_type_t;
+
+typedef struct {
+ save_state_type_t type;
+ union {
+ amd64_smm_state_save_area_t *amd64_state_save;
+ em64t_smm_state_save_area_t *em64t_state_save;
+ em64t101_smm_state_save_area_t *em64t101_state_save;
+ legacy_smm_state_save_area_t *legacy_state_save;
+ };
+} smm_state_save_area_t;
+
+#if !CONFIG(SMM_TSEG)
+void cpu_smi_handler(unsigned int node, smm_state_save_area_t *state_save);
+void northbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save);
+void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save);
+#endif
+
+#endif
diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h
index b8b99ecdab..a9d1ad4d1e 100644
--- a/src/include/cpu/x86/smm.h
+++ b/src/include/cpu/x86/smm.h
@@ -13,10 +13,6 @@
* GNU General Public License for more details.
*/
-/* AMD64 SMM State-Save Area
- * starts @ 0x7e00
- */
-
#ifndef CPU_X86_SMM_H
#define CPU_X86_SMM_H
@@ -32,438 +28,6 @@
#define SMM_ENTRY_OFFSET 0x8000
#define SMM_SAVE_STATE_BEGIN(x) (SMM_ENTRY_OFFSET + (x))
-/* AMD64 x86 SMM State-Save Area
- * starts @ 0x7e00
- */
-#define SMM_AMD64_ARCH_OFFSET 0x7e00
-#define SMM_AMD64_SAVE_STATE_OFFSET \
- SMM_SAVE_STATE_BEGIN(SMM_AMD64_ARCH_OFFSET)
-typedef struct {
- u16 es_selector;
- u16 es_attributes;
- u32 es_limit;
- u64 es_base;
-
- u16 cs_selector;
- u16 cs_attributcs;
- u32 cs_limit;
- u64 cs_base;
-
- u16 ss_selector;
- u16 ss_attributss;
- u32 ss_limit;
- u64 ss_base;
-
- u16 ds_selector;
- u16 ds_attributds;
- u32 ds_limit;
- u64 ds_base;
-
- u16 fs_selector;
- u16 fs_attributfs;
- u32 fs_limit;
- u64 fs_base;
-
- u16 gs_selector;
- u16 gs_attributgs;
- u32 gs_limit;
- u64 gs_base;
-
- u8 reserved0[4];
- u16 gdtr_limit;
- u8 reserved1[2];
- u64 gdtr_base;
-
- u16 ldtr_selector;
- u16 ldtr_attributes;
- u32 ldtr_limit;
- u64 ldtr_base;
-
- u8 reserved2[4];
- u16 idtr_limit;
- u8 reserved3[2];
- u64 idtr_base;
-
- u16 tr_selector;
- u16 tr_attributes;
- u32 tr_limit;
- u64 tr_base;
-
- u64 io_restart_rip;
- u64 io_restart_rcx;
- u64 io_restart_rsi;
- u64 io_restart_rdi;
- u32 smm_io_trap_offset;
- u32 local_smi_status;
-
- u8 io_restart;
- u8 autohalt_restart;
-
- u8 reserved5[6];
-
- u64 efer;
-
- u8 reserved6[36];
-
- u32 smm_revision;
- u32 smbase;
-
- u8 reserved7[68];
-
- u64 cr4;
- u64 cr3;
- u64 cr0;
- u64 dr7;
- u64 dr6;
-
- u64 rflags;
- u64 rip;
- u64 r15;
- u64 r14;
- u64 r13;
- u64 r12;
- u64 r11;
- u64 r10;
- u64 r9;
- u64 r8;
-
- u64 rdi;
- u64 rsi;
- u64 rpb;
- u64 rsp;
- u64 rbx;
- u64 rdx;
- u64 rcx;
- u64 rax;
-} __packed amd64_smm_state_save_area_t;
-
-
-/* Intel Core 2 (EM64T) SMM State-Save Area
- * starts @ 0x7c00
- */
-#define SMM_EM64T_ARCH_OFFSET 0x7c00
-#define SMM_EM64T_SAVE_STATE_OFFSET \
- SMM_SAVE_STATE_BEGIN(SMM_EM64T_ARCH_OFFSET)
-typedef struct {
- u8 reserved0[256];
- u8 reserved1[208];
-
- u32 gdtr_upper_base;
- u32 ldtr_upper_base;
- u32 idtr_upper_base;
-
- u8 reserved2[4];
-
- u64 io_rdi;
- u64 io_rip;
- u64 io_rcx;
- u64 io_rsi;
- u64 cr4;
-
- u8 reserved3[68];
-
- u64 gdtr_base;
- u64 idtr_base;
- u64 ldtr_base;
-
- u8 reserved4[84];
-
- u32 smm_revision;
- u32 smbase;
-
- u16 io_restart;
- u16 autohalt_restart;
-
- u8 reserved5[24];
-
- u64 r15;
- u64 r14;
- u64 r13;
- u64 r12;
- u64 r11;
- u64 r10;
- u64 r9;
- u64 r8;
-
- u64 rax;
- u64 rcx;
- u64 rdx;
- u64 rbx;
-
- u64 rsp;
- u64 rbp;
- u64 rsi;
- u64 rdi;
-
-
- u64 io_mem_addr;
- u32 io_misc_info;
-
- u32 es_sel;
- u32 cs_sel;
- u32 ss_sel;
- u32 ds_sel;
- u32 fs_sel;
- u32 gs_sel;
-
- u32 ldtr_sel;
- u32 tr_sel;
-
- u64 dr7;
- u64 dr6;
- u64 rip;
- u64 efer;
- u64 rflags;
-
- u64 cr3;
- u64 cr0;
-} __packed em64t_smm_state_save_area_t;
-
-
-/* Intel Revision 30100 SMM State-Save Area
- * The following processor architectures use this:
- * - Bay Trail
- */
-#define SMM_EM64T100_ARCH_OFFSET 0x7c00
-#define SMM_EM64T100_SAVE_STATE_OFFSET \
- SMM_SAVE_STATE_BEGIN(SMM_EM64T100_ARCH_OFFSET)
-typedef struct {
- u8 reserved0[256];
- u8 reserved1[208];
-
- u32 gdtr_upper_base;
- u32 ldtr_upper_base;
- u32 idtr_upper_base;
-
- u8 reserved2[4];
-
- u64 io_rdi;
- u64 io_rip;
- u64 io_rcx;
- u64 io_rsi;
-
- u8 reserved3[64];
- u32 cr4;
-
- u8 reserved4[72];
-
- u32 gdtr_base;
- u8 reserved5[4];
- u32 idtr_base;
- u8 reserved6[4];
- u32 ldtr_base;
-
- u8 reserved7[88];
-
- u32 smbase;
- u32 smm_revision;
-
- u16 io_restart;
- u16 autohalt_restart;
-
- u8 reserved8[24];
-
- u64 r15;
- u64 r14;
- u64 r13;
- u64 r12;
- u64 r11;
- u64 r10;
- u64 r9;
- u64 r8;
-
- u64 rax;
- u64 rcx;
- u64 rdx;
- u64 rbx;
-
- u64 rsp;
- u64 rbp;
- u64 rsi;
- u64 rdi;
-
-
- u64 io_mem_addr;
- u32 io_misc_info;
-
- u32 es_sel;
- u32 cs_sel;
- u32 ss_sel;
- u32 ds_sel;
- u32 fs_sel;
- u32 gs_sel;
-
- u32 ldtr_sel;
- u32 tr_sel;
-
- u64 dr7;
- u64 dr6;
- u64 rip;
- u64 efer;
- u64 rflags;
-
- u64 cr3;
- u64 cr0;
-} __packed em64t100_smm_state_save_area_t;
-
-/* Intel Revision 30101 SMM State-Save Area
- * The following processor architectures use this:
- * - SandyBridge
- * - IvyBridge
- * - Haswell
- */
-#define SMM_EM64T101_ARCH_OFFSET 0x7c00
-#define SMM_EM64T101_SAVE_STATE_OFFSET \
- SMM_SAVE_STATE_BEGIN(SMM_EM64T101_ARCH_OFFSET)
-typedef struct {
- u8 reserved0[256];
- u8 reserved1[208];
-
- u32 gdtr_upper_base;
- u32 ldtr_upper_base;
- u32 idtr_upper_base;
-
- u32 io_cf8;
-
- u64 io_rdi;
- u64 io_rip;
- u64 io_rcx;
- u64 io_rsi;
-
- u8 reserved2[52];
- u32 shutdown_auto_restart;
- u8 reserved3[8];
- u32 cr4;
-
- u8 reserved4[72];
-
- u32 gdtr_base;
- u8 reserved5[4];
- u32 idtr_base;
- u8 reserved6[4];
- u32 ldtr_base;
-
- u8 reserved7[56];
- /* EPTP fields are only on Haswell according to BWGs, but Intel was
- * wise and reused the same revision number. */
- u64 eptp;
- u32 eptp_en;
- u32 cs_base;
- u8 reserved8[4];
- u32 iedbase;
-
- u8 reserved9[8];
-
- u32 smbase;
- u32 smm_revision;
-
- u16 io_restart;
- u16 autohalt_restart;
-
- u8 reserved10[24];
-
- u64 r15;
- u64 r14;
- u64 r13;
- u64 r12;
- u64 r11;
- u64 r10;
- u64 r9;
- u64 r8;
-
- u64 rax;
- u64 rcx;
- u64 rdx;
- u64 rbx;
-
- u64 rsp;
- u64 rbp;
- u64 rsi;
- u64 rdi;
-
-
- u64 io_mem_addr;
- u32 io_misc_info;
-
- u32 es_sel;
- u32 cs_sel;
- u32 ss_sel;
- u32 ds_sel;
- u32 fs_sel;
- u32 gs_sel;
-
- u32 ldtr_sel;
- u32 tr_sel;
-
- u64 dr7;
- u64 dr6;
- u64 rip;
- u64 efer;
- u64 rflags;
-
- u64 cr3;
- u64 cr0;
-} __packed em64t101_smm_state_save_area_t;
-
-
-/* Legacy x86 SMM State-Save Area
- * starts @ 0x7e00
- */
-#define SMM_LEGACY_ARCH_OFFSET 0x7e00
-
-typedef struct {
- u8 reserved0[248];
- u32 smbase;
- u32 smm_revision;
- u16 io_restart;
- u16 autohalt_restart;
- u8 reserved1[132];
- u32 gdtbase;
- u8 reserved2[8];
- u32 idtbase;
- u8 reserved3[16];
- u32 es;
- u32 cs;
- u32 ss;
- u32 ds;
- u32 fs;
- u32 gs;
- u32 ldtbase;
- u32 tr;
- u32 dr7;
- u32 dr6;
- u32 eax;
- u32 ecx;
- u32 edx;
- u32 ebx;
- u32 esp;
- u32 ebp;
- u32 esi;
- u32 edi;
- u32 eip;
- u32 eflags;
- u32 cr3;
- u32 cr0;
-} __packed legacy_smm_state_save_area_t;
-
-typedef enum {
- AMD64,
- EM64T,
- EM64T101,
- LEGACY
-} save_state_type_t;
-
-
-typedef struct {
- save_state_type_t type;
- union {
- amd64_smm_state_save_area_t *amd64_state_save;
- em64t_smm_state_save_area_t *em64t_state_save;
- em64t101_smm_state_save_area_t *em64t101_state_save;
- legacy_smm_state_save_area_t *legacy_state_save;
- };
-} smm_state_save_area_t;
-
#define APM_CNT 0xb2
#define APM_CNT_CST_CONTROL 0x85
#define APM_CNT_PST_CONTROL 0x80
@@ -490,13 +54,8 @@ void southbridge_smi_set_eos(void);
void cpu_smi_handler(void);
void northbridge_smi_handler(void);
void southbridge_smi_handler(void);
-#else
-void cpu_smi_handler(unsigned int node, smm_state_save_area_t *state_save);
-void northbridge_smi_handler(unsigned int node,
- smm_state_save_area_t *state_save);
-void southbridge_smi_handler(unsigned int node,
- smm_state_save_area_t *state_save);
-#endif /* CONFIG_SMM_TSEG */
+#endif
+
void mainboard_smi_gpi(u32 gpi_sts);
int mainboard_smi_apmc(u8 data);
void mainboard_smi_sleep(u8 slp_typ);
diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c
index 21818e4c88..d693e4b68c 100644
--- a/src/soc/amd/picasso/cpu.c
+++ b/src/soc/amd/picasso/cpu.c
@@ -20,6 +20,7 @@
#include <cpu/x86/msr.h>
#include <cpu/x86/smm.h>
#include <cpu/amd/msr.h>
+#include <cpu/amd/amd64_save_state.h>
#include <cpu/x86/lapic.h>
#include <device/device.h>
#include <device/pci_ops.h>
diff --git a/src/soc/amd/picasso/smihandler.c b/src/soc/amd/picasso/smihandler.c
index d8438bb366..9eddf853b6 100644
--- a/src/soc/amd/picasso/smihandler.c
+++ b/src/soc/amd/picasso/smihandler.c
@@ -19,6 +19,7 @@
#include <console/console.h>
#include <cpu/x86/smm.h>
#include <cpu/x86/cache.h>
+#include <cpu/amd/amd64_save_state.h>
#include <arch/acpi.h>
#include <arch/hlt.h>
#include <device/pci_def.h>
diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c
index 4684aeaf8c..15777944d4 100644
--- a/src/soc/amd/stoneyridge/cpu.c
+++ b/src/soc/amd/stoneyridge/cpu.c
@@ -20,6 +20,7 @@
#include <cpu/x86/msr.h>
#include <cpu/x86/smm.h>
#include <cpu/amd/msr.h>
+#include <cpu/amd/amd64_save_state.h>
#include <cpu/x86/lapic.h>
#include <device/device.h>
#include <device/pci_ops.h>
diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c
index d8438bb366..9eddf853b6 100644
--- a/src/soc/amd/stoneyridge/smihandler.c
+++ b/src/soc/amd/stoneyridge/smihandler.c
@@ -19,6 +19,7 @@
#include <console/console.h>
#include <cpu/x86/smm.h>
#include <cpu/x86/cache.h>
+#include <cpu/amd/amd64_save_state.h>
#include <arch/acpi.h>
#include <arch/hlt.h>
#include <device/pci_def.h>
diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c
index 9b9b722bb3..9fbcc073c9 100644
--- a/src/soc/intel/apollolake/cpu.c
+++ b/src/soc/intel/apollolake/cpu.c
@@ -30,6 +30,7 @@
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h>
+#include <cpu/intel/em64t100_save_state.h>
#include <device/device.h>
#include <device/pci.h>
#include <fsp/api.h>
diff --git a/src/soc/intel/apollolake/smihandler.c b/src/soc/intel/apollolake/smihandler.c
index 7a3400ed3b..53d2b7e858 100644
--- a/src/soc/intel/apollolake/smihandler.c
+++ b/src/soc/intel/apollolake/smihandler.c
@@ -15,6 +15,7 @@
*/
#include <cpu/x86/smm.h>
+#include <cpu/intel/em64t100_save_state.h>
#include <intelblocks/smihandler.h>
#include <soc/gpio.h>
#include <soc/iomap.h>
diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c
index 952693217c..ebc4c22667 100644
--- a/src/soc/intel/baytrail/cpu.c
+++ b/src/soc/intel/baytrail/cpu.c
@@ -25,6 +25,7 @@
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h>
+#include <cpu/intel/em64t100_save_state.h>
#include <reg_script.h>
#include <soc/iosf.h>
diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c
index 1bc9ed1c34..7de9d960a0 100644
--- a/src/soc/intel/baytrail/smihandler.c
+++ b/src/soc/intel/baytrail/smihandler.c
@@ -20,6 +20,7 @@
#include <console/console.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/smm.h>
+#include <cpu/intel/em64t100_save_state.h>
#include <device/pci_def.h>
#include <elog.h>
#include <halt.h>
diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c
index 1cee4b9ca4..1b1548ad6d 100644
--- a/src/soc/intel/braswell/cpu.c
+++ b/src/soc/intel/braswell/cpu.c
@@ -26,6 +26,7 @@
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h>
+#include <cpu/intel/em64t100_save_state.h>
#include <reg_script.h>
#include <soc/iosf.h>
#include <soc/msr.h>
diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c
index a72330915e..174cd5d7ef 100644
--- a/src/soc/intel/braswell/smihandler.c
+++ b/src/soc/intel/braswell/smihandler.c
@@ -21,6 +21,7 @@
#include <console/console.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/smm.h>
+#include <cpu/intel/em64t100_save_state.h>
#include <device/pci_def.h>
#include <elog.h>
#include <soc/nvs.h>
diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c
index b36b99dd4e..bad158748d 100644
--- a/src/soc/intel/broadwell/smihandler.c
+++ b/src/soc/intel/broadwell/smihandler.c
@@ -23,6 +23,7 @@
#include <cpu/x86/cache.h>
#include <device/pci_def.h>
#include <cpu/x86/smm.h>
+#include <cpu/intel/em64t101_save_state.h>
#include <spi-generic.h>
#include <elog.h>
#include <halt.h>
diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/smmrelocate.c
index 9ea73b2054..228cccd7b1 100644
--- a/src/soc/intel/broadwell/smmrelocate.c
+++ b/src/soc/intel/broadwell/smmrelocate.c
@@ -24,6 +24,7 @@
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h>
+#include <cpu/intel/em64t101_save_state.h>
#include <console/console.h>
#include <soc/cpu.h>
#include <soc/msr.h>
diff --git a/src/soc/intel/cannonlake/smmrelocate.c b/src/soc/intel/cannonlake/smmrelocate.c
index 9a23d5a8f9..45b2ff81ee 100644
--- a/src/soc/intel/cannonlake/smmrelocate.c
+++ b/src/soc/intel/cannonlake/smmrelocate.c
@@ -26,6 +26,7 @@
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h>
+#include <cpu/intel/em64t101_save_state.h>
#include <console/console.h>
#include <intelblocks/smm.h>
#include <soc/cpu.h>
diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c
index abd699ac2b..9e98aae564 100644
--- a/src/soc/intel/common/block/smm/smihandler.c
+++ b/src/soc/intel/common/block/smm/smihandler.c
@@ -20,6 +20,8 @@
#include <console/console.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/smm.h>
+#include <cpu/intel/em64t100_save_state.h>
+#include <cpu/intel/em64t101_save_state.h>
#include <delay.h>
#include <device/pci_def.h>
#include <elog.h>
diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c
index 067f59fb3a..bda6d1defc 100644
--- a/src/soc/intel/denverton_ns/cpu.c
+++ b/src/soc/intel/denverton_ns/cpu.c
@@ -22,6 +22,7 @@
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h>
+#include <cpu/intel/em64t100_save_state.h>
#include <cpu/intel/turbo.h>
#include <device/device.h>
#include <device/pci.h>
diff --git a/src/soc/intel/denverton_ns/smihandler.c b/src/soc/intel/denverton_ns/smihandler.c
index 4d748b2a71..cba659a7a6 100644
--- a/src/soc/intel/denverton_ns/smihandler.c
+++ b/src/soc/intel/denverton_ns/smihandler.c
@@ -23,6 +23,7 @@
#include <console/console.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/smm.h>
+#include <cpu/intel/em64t100_save_state.h>
#include <device/pci_def.h>
#include <elog.h>
#include <intelblocks/fast_spi.h>
diff --git a/src/soc/intel/fsp_baytrail/cpu.c b/src/soc/intel/fsp_baytrail/cpu.c
index 15dc851b96..769f4d4d76 100644
--- a/src/soc/intel/fsp_baytrail/cpu.c
+++ b/src/soc/intel/fsp_baytrail/cpu.c
@@ -25,6 +25,7 @@
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h>
+#include <cpu/intel/em64t100_save_state.h>
#include <reg_script.h>
#include <soc/msr.h>
diff --git a/src/soc/intel/fsp_baytrail/smihandler.c b/src/soc/intel/fsp_baytrail/smihandler.c
index f2abd9975a..2a7376ad7d 100644
--- a/src/soc/intel/fsp_baytrail/smihandler.c
+++ b/src/soc/intel/fsp_baytrail/smihandler.c
@@ -20,6 +20,7 @@
#include <console/console.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/smm.h>
+#include <cpu/intel/em64t100_save_state.h>
#include <device/pci_def.h>
#include <elog.h>
#include <halt.h>
diff --git a/src/soc/intel/fsp_broadwell_de/smmrelocate.c b/src/soc/intel/fsp_broadwell_de/smmrelocate.c
index 57ba432806..13d48c067c 100644
--- a/src/soc/intel/fsp_broadwell_de/smmrelocate.c
+++ b/src/soc/intel/fsp_broadwell_de/smmrelocate.c
@@ -23,6 +23,7 @@
#include <cpu/x86/mp.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h>
+#include <cpu/intel/em64t101_save_state.h>
#include <console/console.h>
#include <device/pci_ops.h>
#include <soc/lpc.h>
diff --git a/src/soc/intel/icelake/smmrelocate.c b/src/soc/intel/icelake/smmrelocate.c
index edda5400c0..679aaa2af7 100644
--- a/src/soc/intel/icelake/smmrelocate.c
+++ b/src/soc/intel/icelake/smmrelocate.c
@@ -25,6 +25,7 @@
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h>
+#include <cpu/intel/em64t101_save_state.h>
#include <console/console.h>
#include <intelblocks/smm.h>
#include <soc/cpu.h>
diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c
index 9bc599a3cd..34497fceeb 100644
--- a/src/soc/intel/skylake/smmrelocate.c
+++ b/src/soc/intel/skylake/smmrelocate.c
@@ -25,6 +25,7 @@
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h>
+#include <cpu/intel/em64t101_save_state.h>
#include <console/console.h>
#include <intelblocks/smm.h>
#include <soc/cpu.h>
diff --git a/src/southbridge/amd/agesa/hudson/smihandler.c b/src/southbridge/amd/agesa/hudson/smihandler.c
index 1b9442b1b6..2b2606d1f4 100644
--- a/src/southbridge/amd/agesa/hudson/smihandler.c
+++ b/src/southbridge/amd/agesa/hudson/smihandler.c
@@ -20,6 +20,7 @@
#include <arch/io.h>
#include <cpu/x86/smm.h>
+#include <cpu/x86/smi_deprecated.h>
#include "hudson.h"
#include "smi.h"
diff --git a/src/southbridge/amd/pi/hudson/smihandler.c b/src/southbridge/amd/pi/hudson/smihandler.c
index 1b9442b1b6..2b2606d1f4 100644
--- a/src/southbridge/amd/pi/hudson/smihandler.c
+++ b/src/southbridge/amd/pi/hudson/smihandler.c
@@ -20,6 +20,7 @@
#include <arch/io.h>
#include <cpu/x86/smm.h>
+#include <cpu/x86/smi_deprecated.h>
#include "hudson.h"
#include "smi.h"
diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c
index 374a9d933e..9df7b1c14e 100644
--- a/src/southbridge/intel/bd82x6x/smihandler.c
+++ b/src/southbridge/intel/bd82x6x/smihandler.c
@@ -21,6 +21,7 @@
#include <cpu/x86/cache.h>
#include <device/pci_def.h>
#include <cpu/x86/smm.h>
+#include <cpu/intel/em64t101_save_state.h>
#include <elog.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <southbridge/intel/bd82x6x/me.h>
diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h
index eb74aa57ce..cea5c82502 100644
--- a/src/southbridge/intel/common/pmutil.h
+++ b/src/southbridge/intel/common/pmutil.h
@@ -18,6 +18,7 @@
#define INTEL_COMMON_PMUTIL_H
#include <cpu/x86/smm.h>
+#include <cpu/intel/em64t101_save_state.h>
#define D31F0_PMBASE 0x40
#define D31F0_GEN_PMCON_1 0xa0
diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c
index 8a16aaaddd..597f1a7421 100644
--- a/src/southbridge/intel/common/smihandler.c
+++ b/src/southbridge/intel/common/smihandler.c
@@ -22,6 +22,8 @@
#include <cpu/x86/cache.h>
#include <device/pci_def.h>
#include <cpu/x86/smm.h>
+#include <cpu/intel/em64t101_save_state.h>
+#include <cpu/x86/smi_deprecated.h>
#include <elog.h>
#include <halt.h>
#include <pc80/mc146818rtc.h>
diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c
index 944adc32b4..3bfe4024bb 100644
--- a/src/southbridge/intel/i82801dx/smihandler.c
+++ b/src/southbridge/intel/i82801dx/smihandler.c
@@ -20,6 +20,7 @@
#include <console/console.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/smm.h>
+#include <cpu/x86/smi_deprecated.h>
#include <device/pci_def.h>
#include "i82801dx.h"
diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c
index 208075bbea..a254bd7c47 100644
--- a/src/southbridge/intel/ibexpeak/smihandler.c
+++ b/src/southbridge/intel/ibexpeak/smihandler.c
@@ -21,6 +21,7 @@
#include <cpu/x86/cache.h>
#include <device/pci_def.h>
#include <cpu/x86/smm.h>
+#include <cpu/intel/em64t101_save_state.h>
#include <elog.h>
#include <halt.h>
#include <pc80/mc146818rtc.h>
diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c
index 88c599f782..de2866e08c 100644
--- a/src/southbridge/intel/lynxpoint/smihandler.c
+++ b/src/southbridge/intel/lynxpoint/smihandler.c
@@ -22,6 +22,7 @@
#include <cpu/x86/cache.h>
#include <device/pci_def.h>
#include <cpu/x86/smm.h>
+#include <cpu/intel/em64t101_save_state.h>
#include <elog.h>
#include <halt.h>
#include <pc80/mc146818rtc.h>