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authorLin Huang <hl@rock-chips.com>2017-11-16 09:52:27 +0800
committerJulius Werner <jwerner@chromium.org>2017-11-28 19:14:25 +0000
commitecd600a0caa18b0346e4b8024aae2263db0d7821 (patch)
tree225ac9e80b1f21e1609e303557a2553321f485a9
parent5220e5fba6606224976e8a540c7a07d447d8b3d8 (diff)
downloadcoreboot-ecd600a0caa18b0346e4b8024aae2263db0d7821.tar.xz
rockchip/rk3399: mipi: Fix LOOP_DIV_HIGH_SEL to be 4 bits wide
Accroding to datasheet, feedback divider register high value is only 4 bit, it currently uses 5 bit, so correct it. Change-Id: I1fe9fc076b712f27407c5f2735b15e64fb55e72e Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/22478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
-rw-r--r--src/soc/rockchip/rk3399/include/soc/mipi.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/rockchip/rk3399/include/soc/mipi.h b/src/soc/rockchip/rk3399/include/soc/mipi.h
index 2dfbc521d2..bccaf287d3 100644
--- a/src/soc/rockchip/rk3399/include/soc/mipi.h
+++ b/src/soc/rockchip/rk3399/include/soc/mipi.h
@@ -197,7 +197,7 @@ check_member(rk_mipi_regs, dsi_int_msk1, 0xc8);
#define LOW_PROGRAM_EN 0
#define HIGH_PROGRAM_EN BIT(7)
#define LOOP_DIV_LOW_SEL(val) ((val - 1) & 0x1f)
-#define LOOP_DIV_HIGH_SEL(val) (((val - 1) >> 5) & 0x1f)
+#define LOOP_DIV_HIGH_SEL(val) (((val - 1) >> 5) & 0xf)
#define PLL_LOOP_DIV_EN BIT(5)
#define PLL_INPUT_DIV_EN BIT(4)