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| author | Nico Huber <nico.huber@secunet.com> | 2017-03-30 17:45:36 +0200 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2017-06-06 17:19:50 +0200 |
| commit | ed9c9ce26841a958dac3517646f655e2a1887a5b (patch) | |
| tree | ab7a04ac44e5ca2a9d79b05e27d1c1f3b6622668 | |
| parent | ac826c8fd7b616f8b65a268e7474d8c0cf84f93f (diff) | |
| download | coreboot-ed9c9ce26841a958dac3517646f655e2a1887a5b.tar.xz | |
inteltool: Add first Skylake PCI IDs
Change-Id: Ia5ef6b04f01e381174a4d8f73ddafeb18d488803
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
| -rw-r--r-- | util/inteltool/inteltool.c | 2 | ||||
| -rw-r--r-- | util/inteltool/inteltool.h | 2 |
2 files changed, 4 insertions, 0 deletions
diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index cefce7e27e..fb24f74793 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -111,6 +111,7 @@ static const struct { { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U, "5th generation (Broadwell family) Core Processor ULT" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL, "Bay Trail" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST, "6th generation (Skylake-S/H family) Core Processor (Workstation)" }, /* Southbridges (LPC controllers) */ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "371AB/EB/MB" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10, "ICH10" }, @@ -198,6 +199,7 @@ static const struct { "Wildcat Point Low Power SKU" }, { PCI_VENDOR_ID_INTEL, 0x2310, "DH89xxCC" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_LPC, "Bay Trail" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CM236, "CM236" }, }; #ifndef __DARWIN__ diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 3e534b5def..2ff08717fd 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -136,6 +136,7 @@ static inline uint32_t inl(unsigned port) #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE 0x9c45 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_PREM 0x9cc3 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP 0x9cc5 +#define PCI_DEVICE_ID_INTEL_CM236 0xa150 #define PCI_DEVICE_ID_INTEL_82810 0x7120 #define PCI_DEVICE_ID_INTEL_82810_DC 0x7122 #define PCI_DEVICE_ID_INTEL_82810E_DC 0x7124 @@ -204,6 +205,7 @@ static inline uint32_t inl(unsigned port) #define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3 0x0c08 /* Haswell (Xeon E3 v3) */ #define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U 0x0a04 /* Haswell-ULT */ #define PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U 0x1604 /* Broadwell-ULT */ +#define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST 0x1918 #define ARRAY_SIZE(a) ((int)(sizeof(a) / sizeof((a)[0]))) |