diff options
| author | V Sowmya <v.sowmya@intel.com> | 2018-03-15 21:38:30 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-03-23 08:54:33 +0000 |
| commit | efce854fc69f441f651d3e5a1b9482f366967b01 (patch) | |
| tree | bbc428b205b011d84957b4711b94f9021c062e75 | |
| parent | 57afc5e0f2309ba9f7fbd171642f04c6da9d9976 (diff) | |
| download | coreboot-efce854fc69f441f651d3e5a1b9482f366967b01.tar.xz | |
mb/intel/kblrvp8: Add KBLRVP8 support
Add the config for setting SPD DIMM size to 512 bytes
for KBLRVP8 with DDR4 memory. Configure the DIMM1 memory
SPD data for channel0 and channel1. Set the UserBd UPD to
BOARD_TYPE_DESKTOP for kblrvp8.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I985968d331991884050c3920ec9798cd4cb371c7
Reviewed-on: https://review.coreboot.org/25194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
| -rw-r--r-- | src/mainboard/intel/kblrvp/Kconfig | 3 | ||||
| -rw-r--r-- | src/mainboard/intel/kblrvp/romstage.c | 14 |
2 files changed, 13 insertions, 4 deletions
diff --git a/src/mainboard/intel/kblrvp/Kconfig b/src/mainboard/intel/kblrvp/Kconfig index 5ca46e19e1..bbeb12987e 100644 --- a/src/mainboard/intel/kblrvp/Kconfig +++ b/src/mainboard/intel/kblrvp/Kconfig @@ -98,4 +98,7 @@ config PRERAM_CBMEM_CONSOLE_SIZE hex default 0xd00 +config DIMM_SPD_SIZE + int + default 512 if BOARD_INTEL_KBLRVP8 #DDR4 endif diff --git a/src/mainboard/intel/kblrvp/romstage.c b/src/mainboard/intel/kblrvp/romstage.c index 7bfbe1c744..a29a4afc44 100644 --- a/src/mainboard/intel/kblrvp/romstage.c +++ b/src/mainboard/intel/kblrvp/romstage.c @@ -49,7 +49,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) mem_cfg->MemorySpdDataLen = region_device_sz(&spd_rdev); /* Memory leak is ok since we have memory mapped boot media */ mem_cfg->MemorySpdPtr00 = (uintptr_t)rdev_mmap_full(&spd_rdev); - } else { /* for CONFIG_BOARD_INTEL_KBLRVP7 */ + } else { /* CONFIG_BOARD_INTEL_KBLRVP7 and CONFIG_BOARD_INTEL_KBLRVP8 */ struct spd_block blk = { .addr_map = { 0x50, 0x51, 0x52, 0x53, }, }; @@ -57,9 +57,15 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) mem_cfg->DqPinsInterleaved = 1; get_spd_smbus(&blk); mem_cfg->MemorySpdDataLen = blk.len; - mem_cfg->MemorySpdPtr00 = (u32)blk.spd_array[0]; - } - mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; + mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; + mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[2]; + if (IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP8)) { + mem_cfg->MemorySpdPtr01 = (uintptr_t)blk.spd_array[1]; + mem_cfg->MemorySpdPtr11 = (uintptr_t)blk.spd_array[3]; + } + } mupd->FspmTestConfig.DmiVc1 = 1; + if (IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP8)) + mem_cfg->UserBd = BOARD_TYPE_DESKTOP; } |