superio/ite/*: Factor out generic romstage component

Following the reasoning of:
cf7b498 superio/fintek/*: Factor out generic romstage component

Change-Id: I4c0a9a5a7786eb8fcb0c3ed6251c7fe9bbbadae7
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5585
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>

50 files changed, 247 insertions, 386 deletions

diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c
index 7a0c8f936b..c9a04f5eef 100644
--- a/src/mainboard/amd/dbm690t/romstage.c
+++ b/src/mainboard/amd/dbm690t/romstage.c
@@ -30,7 +30,8 @@
 #include "lib/delay.c"
 #include "cpu/x86/lapic.h"
 #include "northbridge/amd/amdk8/reset_test.c"
-#include "superio/ite/it8712f/early_serial.c"
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8712f/it8712f.h>
 #include <spd.h>
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
@@ -38,6 +39,8 @@
 #include "southbridge/amd/sb600/early_setup.c"
 #include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */
 
+#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
+
 static void memreset(int controllers, const struct mem_controller *ctrl) { }
 static void activate_spd_rom(const struct mem_controller *ctrl) { }
 
@@ -80,8 +83,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	enable_rs690_dev8();
 	sb600_lpc_init();
 
-	/* it8712f_enable_serial does not use its 1st parameter. */
-	it8712f_enable_serial(0, CONFIG_TTYS0_BASE);
+	ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 
 	console_init();
 
diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c
index 93870c5367..00223aed74 100644
--- a/src/mainboard/amd/mahogany/romstage.c
+++ b/src/mainboard/amd/mahogany/romstage.c
@@ -31,7 +31,8 @@
 #include "lib/delay.c"
 #include "cpu/x86/lapic.h"
 #include "northbridge/amd/amdk8/reset_test.c"
-#include "superio/ite/it8718f/early_serial.c"
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8718f/it8718f.h>
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 #include "southbridge/amd/rs780/early_setup.c"
@@ -39,6 +40,8 @@
 #include "southbridge/amd/sb700/smbus.h"
 #include "northbridge/amd/amdk8/debug.c" /* After sb700/early_setup.c! */
 
+#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1)
+
 static void memreset(int controllers, const struct mem_controller *ctrl) { }
 static void activate_spd_rom(const struct mem_controller *ctrl) { }
 
@@ -81,7 +84,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	enable_rs780_dev8();
 	sb7xx_51xx_lpc_init();
 
-	it8718f_enable_serial(0, CONFIG_TTYS0_BASE);
+	ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 
 	console_init();
 
diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index 06deb1880e..278a3bd50f 100644
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -41,7 +41,8 @@
 #include "northbridge/amd/amdfam10/reset_test.c"
 #include <console/loglevel.h>
 #include "cpu/x86/bist.h"
-#include "superio/ite/it8718f/early_serial.c"
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8718f/it8718f.h>
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
 #include "southbridge/amd/rs780/early_setup.c"
@@ -50,6 +51,8 @@
 #include "northbridge/amd/amdfam10/debug.c"
 #include <spd.h>
 
+#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1)
+
 static void activate_spd_rom(const struct mem_controller *ctrl) { }
 
 static int spd_read_byte(u32 device, u32 address)
@@ -95,7 +98,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	enable_rs780_dev8();
 	sb7xx_51xx_lpc_init();
 
-	it8718f_enable_serial(0, CONFIG_TTYS0_BASE);
+	ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 
 	console_init();
 
diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c
index 30e56d4bb4..6e28cbdd33 100644
--- a/src/mainboard/amd/tilapia_fam10/romstage.c
+++ b/src/mainboard/amd/tilapia_fam10/romstage.c
@@ -41,7 +41,8 @@
 #include "northbridge/amd/amdfam10/reset_test.c"
 #include <console/loglevel.h>
 #include "cpu/x86/bist.h"
-#include "superio/ite/it8718f/early_serial.c"
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8718f/it8718f.h>
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
 #include "southbridge/amd/rs780/early_setup.c"
@@ -49,6 +50,8 @@
 #include "southbridge/amd/sb700/smbus.h"
 #include "northbridge/amd/amdfam10/debug.c"
 
+#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1)
+
 static void activate_spd_rom(const struct mem_controller *ctrl) { }
 
 static int spd_read_byte(u32 device, u32 address)
@@ -95,7 +98,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	enable_rs780_dev8();
 	sb7xx_51xx_lpc_init();
 
-	it8718f_enable_serial(0, CONFIG_TTYS0_BASE);
+	ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 
 	console_init();
 
diff --git a/src/mainboard/asus/a8n_e/romstage.c b/src/mainboard/asus/a8n_e/romstage.c
index 29f425a225..c0fa6a52fd 100644
--- a/src/mainboard/asus/a8n_e/romstage.c
+++ b/src/mainboard/asus/a8n_e/romstage.c
@@ -21,8 +21,9 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-/* Used by it8712f_enable_serial(). */
+/* Used by ite_enable_serial(). */
 #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
+#define CLKIN_DEV PNP_DEV(0x2e, IT8712F_GPIO)
 
 #include <stdint.h>
 #include <string.h>
@@ -33,7 +34,8 @@
 #include <pc80/mc146818rtc.h>
 #include "cpu/x86/lapic.h"
 #include "northbridge/amd/amdk8/reset_test.c"
-#include "superio/ite/it8712f/early_serial.c"
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8712f/it8712f.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include <console/console.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
@@ -103,8 +105,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	if (bist == 0)
 		bsp_apicid = init_cpus(cpu_init_detectedx);
 
-	it8712f_24mhz_clkin();
-	it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24);
+	ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	console_init();
 
 	/* Halt if there was a built in self test failure */
diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c
index 4aa4b04e4a..487f0684a1 100644
--- a/src/mainboard/asus/f2a85-m/romstage.c
+++ b/src/mainboard/asus/f2a85-m/romstage.c
@@ -36,16 +36,19 @@
 #include <southbridge/amd/agesa/hudson/smbus.h>
 #include <stdint.h>
 #include <string.h>
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8712f/it8712f.h>
 /* TODO: remove .c includes */
 #include <drivers/pc80/i8254.c>
 #include <drivers/pc80/i8259.c>
-#include <superio/ite/it8712f/early_serial.c>
 
 #define MMIO_NON_POSTED_START 0xfed00000
 #define MMIO_NON_POSTED_END   0xfedfffff
 #define SB_MMIO 0xFED80000
 #define SB_MMIO_MISC32(x) *(volatile u32 *)(SB_MMIO + 0xE00 + (x))
 
+#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
+
 static void sbxxx_enable_48mhzout(void)
 {
 	/* most likely programming to 48MHz out signal */
@@ -95,7 +98,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		/* enable SIO clock */
 		sbxxx_enable_48mhzout();
 		it8712f_kill_watchdog();
-		it8712f_enable_serial(0, CONFIG_TTYS0_BASE);
+		ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 		it8712f_enable_3vsbsw();
 		console_init();
 
diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c
index 6892b287bb..d12b77c5be 100644
--- a/src/mainboard/asus/m2n-e/romstage.c
+++ b/src/mainboard/asus/m2n-e/romstage.c
@@ -37,6 +37,7 @@
 #include <spd.h>
 #include "cpu/x86/lapic.h"
 #include "northbridge/amd/amdk8/reset_test.c"
+#include <superio/ite/common/ite.h>
 #include <superio/ite/it8716f/it8716f.h>
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/debug.c"
@@ -104,8 +105,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	if (bist == 0)
 		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 
-	it8716f_conf_clkin(CLKIN_DEV, IT8716F_UART_CLK_PREDIVIDE_24);
-	it8716f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24);
+	ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 
 	setup_mb_resource_map();
 	report_bist_failure(bist);
diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c
index ef0ce87726..0085bb42d5 100644
--- a/src/mainboard/asus/m2v-mx_se/romstage.c
+++ b/src/mainboard/asus/m2v-mx_se/romstage.c
@@ -38,7 +38,8 @@ unsigned int get_sbdn(unsigned bus);
 #include "lib/delay.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
-#include "superio/ite/it8712f/early_serial.c"
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8712f/it8712f.h>
 #include "southbridge/via/vt8237r/early_smbus.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
@@ -127,7 +128,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	int needs_reset = 0;
 	struct sys_info *sysinfo = &sysinfo_car;
 
-	it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	it8712f_kill_watchdog();
 	it8712f_enable_3vsbsw();
 	console_init();
diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c
index 1ca145d704..acf8f9166e 100644
--- a/src/mainboard/asus/m2v/romstage.c
+++ b/src/mainboard/asus/m2v/romstage.c
@@ -38,7 +38,8 @@ unsigned int get_sbdn(unsigned bus);
 #include "lib/delay.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
-#include "superio/ite/it8712f/early_serial.c"
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8712f/it8712f.h>
 #include "southbridge/via/vt8237r/early_smbus.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
@@ -46,6 +47,7 @@ unsigned int get_sbdn(unsigned bus);
 
 #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
 #define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO)
+#define CLKIN_DEV PNP_DEV(0x2e, IT8712F_GPIO)
 
 #define IT8712F_GPIO_BASE		0x0a20
 
@@ -163,15 +165,13 @@ static void m2v_it8712f_gpio_init(void)
 	 * 0xc0=0x17, 0xc8=0x17 gpio port 1 select & output enable
 	 * 0xc4=0xc1, 0xcc=0xc1 gpio port 5 select & output enable
 	 */
-	it8712f_enter_conf();
 	giv = gpio_init_data;
 	while (giv->addr) {
 		printk(BIOS_SPEW, "it8712f gpio: %02x=%02x\n",
 				giv->addr, giv->val);
-		it8712f_sio_write(IT8712F_GPIO, giv->addr, giv->val);
+		ite_reg_write(IT8712F_GPIO, giv->addr, giv->val);
 		giv++;
 	}
-	it8712f_exit_conf();
 
 	printk(BIOS_INFO, "it8712f gpio: Setting DDR2 voltage to 1.80V\n");
 	/*
@@ -225,8 +225,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	int needs_reset = 0;
 	struct sys_info *sysinfo = &sysinfo_car;
 
-	it8712f_24mhz_clkin();
-	it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24);
+	ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	it8712f_kill_watchdog();
 	console_init();
 	enable_rom_decode();
diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c
index 18c6f18151..93810d29b8 100644
--- a/src/mainboard/asus/m4a78-em/romstage.c
+++ b/src/mainboard/asus/m4a78-em/romstage.c
@@ -41,7 +41,8 @@
 #include "northbridge/amd/amdfam10/reset_test.c"
 #include <console/loglevel.h>
 #include "cpu/x86/bist.h"
-#include "superio/ite/it8712f/early_serial.c"
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8712f/it8712f.h>
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
 #include "southbridge/amd/rs780/early_setup.c"
@@ -49,6 +50,8 @@
 #include "southbridge/amd/sb700/smbus.h"
 #include "northbridge/amd/amdfam10/debug.c"
 
+#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
+
 static void activate_spd_rom(const struct mem_controller *ctrl) { }
 
 static int spd_read_byte(u32 device, u32 address)
@@ -95,7 +98,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	enable_rs780_dev8();
 	sb7xx_51xx_lpc_init();
 
-	it8712f_enable_serial(0, CONFIG_TTYS0_BASE);
+	ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	it8712f_kill_watchdog();
 
 	console_init();
diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c
index 660ab0f4cb..b360636d1b 100644
--- a/src/mainboard/asus/m4a785-m/romstage.c
+++ b/src/mainboard/asus/m4a785-m/romstage.c
@@ -41,7 +41,8 @@
 #include "northbridge/amd/amdfam10/reset_test.c"
 #include <console/loglevel.h>
 #include "cpu/x86/bist.h"
-#include "superio/ite/it8712f/early_serial.c"
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8712f/it8712f.h>
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
 #include "southbridge/amd/rs780/early_setup.c"
@@ -49,6 +50,8 @@
 #include "southbridge/amd/sb700/smbus.h"
 #include "northbridge/amd/amdfam10/debug.c"
 
+#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
+
 static void activate_spd_rom(const struct mem_controller *ctrl) { }
 
 static int spd_read_byte(u32 device, u32 address)
@@ -95,7 +98,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	enable_rs780_dev8();
 	sb7xx_51xx_lpc_init();
 
-	it8712f_enable_serial(0, CONFIG_TTYS0_BASE);
+	ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	it8712f_kill_watchdog();
 
 	console_init();
diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c
index 94a1e4e596..9fca93feca 100644
--- a/src/mainboard/asus/m5a88-v/romstage.c
+++ b/src/mainboard/asus/m5a88-v/romstage.c
@@ -41,6 +41,7 @@
 #include "northbridge/amd/amdfam10/reset_test.c"
 #include <console/loglevel.h>
 #include "cpu/x86/bist.h"
+#include <superio/ite/common/ite.h>
 #include <superio/ite/it8721f/it8721f.h>
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
@@ -100,7 +101,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	enable_rs780_dev8();
 	sb800_clk_output_48Mhz();
 
-	it8721f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	console_init();
 	printk(BIOS_DEBUG, "\n");
 
diff --git a/src/mainboard/ecs/p6iwp-fe/romstage.c b/src/mainboard/ecs/p6iwp-fe/romstage.c
index 1ebdeddea0..c014c5785a 100644
--- a/src/mainboard/ecs/p6iwp-fe/romstage.c
+++ b/src/mainboard/ecs/p6iwp-fe/romstage.c
@@ -30,13 +30,17 @@
 #include "northbridge/intel/i82810/raminit.h"
 #include "drivers/pc80/udelay_io.c"
 #include "cpu/x86/bist.h"
-#include "superio/ite/it8712f/early_serial.c"
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8712f/it8712f.h>
 #include <lib.h>
 
+#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
+#define CLKIN_DEV PNP_DEV(0x2e, IT8712F_GPIO)
+
 void main(unsigned long bist)
 {
-	it8712f_24mhz_clkin();
-	it8712f_enable_serial(0, CONFIG_TTYS0_BASE); // Does not use its 1st parameter
+	ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24);
+	ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	console_init();
 	report_bist_failure(bist);
 	enable_smbus();
diff --git a/src/mainboard/gigabyte/ga-6bxc/romstage.c b/src/mainboard/gigabyte/ga-6bxc/romstage.c
index 89761c93ce..1b2e29b9ff 100644
--- a/src/mainboard/gigabyte/ga-6bxc/romstage.c
+++ b/src/mainboard/gigabyte/ga-6bxc/romstage.c
@@ -30,8 +30,7 @@
 #include "drivers/pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "cpu/x86/bist.h"
-void it8671f_48mhz_clkin(void);
-#include "superio/ite/it8671f/early_serial.c"
+#include <superio/ite/it8671f/it8671f.h>
 #include <lib.h>
 
 #define SERIAL_DEV PNP_DEV(0x3f0, IT8671F_SP1)
diff --git a/src/mainboard/gigabyte/ga-6bxe/romstage.c b/src/mainboard/gigabyte/ga-6bxe/romstage.c
index 85a899a4a3..c3926f0964 100644
--- a/src/mainboard/gigabyte/ga-6bxe/romstage.c
+++ b/src/mainboard/gigabyte/ga-6bxe/romstage.c
@@ -30,8 +30,7 @@
 #include "drivers/pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "cpu/x86/bist.h"
-static void it8671f_48mhz_clkin(void);
-#include "superio/ite/it8671f/early_serial.c"
+#include <superio/ite/it8671f/it8671f.h>
 #include <lib.h>
 
 #define SERIAL_DEV PNP_DEV(0x3f0, IT8671F_SP1)
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
index 86158c8853..10bbb6f361 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
@@ -38,6 +38,7 @@
 #include "lib/delay.c"
 #include "cpu/x86/lapic.h"
 #include "northbridge/amd/amdk8/reset_test.c"
+#include <superio/ite/common/ite.h>
 #include <superio/ite/it8716f/it8716f.h>
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/debug.c"
@@ -125,8 +126,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         if (bist == 0)
 		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 
-	it8716f_conf_clkin(CLKIN_DEV, IT8716F_UART_CLK_PREDIVIDE_48);
-	it8716f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48);
+	ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 
         setup_mb_resource_map();
 
diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c
index 44dda27c57..b2e1d70477 100644
--- a/src/mainboard/gigabyte/m57sli/romstage.c
+++ b/src/mainboard/gigabyte/m57sli/romstage.c
@@ -35,6 +35,7 @@
 #include "lib/delay.c"
 #include "cpu/x86/lapic.h"
 #include "northbridge/amd/amdk8/reset_test.c"
+#include <superio/ite/common/ite.h>
 #include <superio/ite/it8716f/it8716f.h>
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/debug.c"
@@ -133,8 +134,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  	it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	pnp_exit_ext_func_mode(SERIAL_DEV);
 #endif
-	it8716f_conf_clkin(CLKIN_DEV, IT8716F_UART_CLK_PREDIVIDE_48);
-	it8716f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48);
+	ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 
         setup_mb_resource_map();
 
diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c
index ecee35b530..451cb7956c 100644
--- a/src/mainboard/gigabyte/ma785gm/romstage.c
+++ b/src/mainboard/gigabyte/ma785gm/romstage.c
@@ -37,7 +37,8 @@
 #include "northbridge/amd/amdfam10/reset_test.c"
 #include <console/loglevel.h>
 #include "cpu/x86/bist.h"
-#include "superio/ite/it8718f/early_serial.c"
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8718f/it8718f.h>
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
 #include "southbridge/amd/rs780/early_setup.c"
@@ -45,6 +46,8 @@
 #include "southbridge/amd/sb700/smbus.h"
 #include "northbridge/amd/amdfam10/debug.c"
 
+#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1)
+
 static void activate_spd_rom(const struct mem_controller *ctrl) { }
 
 static int spd_read_byte(u32 device, u32 address)
@@ -91,7 +94,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	enable_rs780_dev8();
 	sb7xx_51xx_lpc_init();
 
-	it8718f_enable_serial(0, CONFIG_TTYS0_BASE);
+	ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	it8718f_disable_reboot();
 	console_init();
 
diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c
index ecee35b530..451cb7956c 100644
--- a/src/mainboard/gigabyte/ma785gmt/romstage.c
+++ b/src/mainboard/gigabyte/ma785gmt/romstage.c
@@ -37,7 +37,8 @@
 #include "northbridge/amd/amdfam10/reset_test.c"
 #include <console/loglevel.h>
 #include "cpu/x86/bist.h"
-#include "superio/ite/it8718f/early_serial.c"
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8718f/it8718f.h>
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
 #include "southbridge/amd/rs780/early_setup.c"
@@ -45,6 +46,8 @@
 #include "southbridge/amd/sb700/smbus.h"
 #include "northbridge/amd/amdfam10/debug.c"
 
+#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1)
+
 static void activate_spd_rom(const struct mem_controller *ctrl) { }
 
 static int spd_read_byte(u32 device, u32 address)
@@ -91,7 +94,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	enable_rs780_dev8();
 	sb7xx_51xx_lpc_init();
 
-	it8718f_enable_serial(0, CONFIG_TTYS0_BASE);
+	ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	it8718f_disable_reboot();
 	console_init();
 
diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c
index bd9011e74d..bfc50b6c5d 100644
--- a/src/mainboard/gigabyte/ma78gm/romstage.c
+++ b/src/mainboard/gigabyte/ma78gm/romstage.c
@@ -41,7 +41,8 @@
 #include "northbridge/amd/amdfam10/reset_test.c"
 #include <console/loglevel.h>
 #include "cpu/x86/bist.h"
-#include "superio/ite/it8718f/early_serial.c"
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8718f/it8718f.h>
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
 #include "southbridge/amd/rs780/early_setup.c"
@@ -49,6 +50,8 @@
 #include "southbridge/amd/sb700/smbus.h"
 #include "northbridge/amd/amdfam10/debug.c"
 
+#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1)
+
 static void activate_spd_rom(const struct mem_controller *ctrl) { }
 
 static int spd_read_byte(u32 device, u32 address)
@@ -95,7 +98,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	enable_rs780_dev8();
 	sb7xx_51xx_lpc_init();
 
-	it8718f_enable_serial(0, CONFIG_TTYS0_BASE);
+	ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	it8718f_disable_reboot();
 
 	console_init();
diff --git a/src/mainboard/lippert/hurricane-lx/romstage.c b/src/mainboard/lippert/hurricane-lx/romstage.c
index 95ea27dad2..063721b059 100644
--- a/src/mainboard/lippert/hurricane-lx/romstage.c
+++ b/src/mainboard/lippert/hurricane-lx/romstage.c
@@ -35,9 +35,13 @@
 #include <spd.h>
 #include "southbridge/amd/cs5536/early_smbus.c"
 #include "southbridge/amd/cs5536/early_setup.c"
-#include "superio/ite/it8712f/early_serial.c"
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8712f/it8712f.h>
 #include "northbridge/amd/lx/raminit.h"
 
+#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
+#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO)
+
 /* Bit0 enables Spread Spectrum. */
 #define SMC_CONFIG	0x01
 
@@ -77,7 +81,6 @@ static int smc_send_config(unsigned char config_data)
 #include "cpu/amd/geode_lx/msrinit.c"
 
 static const u16 sio_init_table[] = { // hi=data, lo=index
-	0x0707,		// select LDN 7 (GPIO, SPI, watchdog, ...)
 	0x042C,		// disable ATXPG; VIN6 enabled, FAN4/5 disabled, VIN7,VIN3 enabled
 	0x1423,		// don't delay PoWeROK1/2
 	0x9072,		// watchdog triggers PWROK, counts seconds
@@ -101,13 +104,10 @@ static void mb_gpio_init(void)
 	int i;
 
 	/* Init Super I/O WDT, GPIOs. Done early, WDT init may trigger reset! */
-	it8712f_enter_conf();
 	for (i = 0; i < ARRAY_SIZE(sio_init_table); i++) {
-		u16 val = sio_init_table[i];
-		outb((u8)val, SIO_INDEX);
-		outb(val >> 8, SIO_DATA);
+		u16 reg = sio_init_table[i];
+		ite_reg_write(GPIO_DEV, (u8) reg, (reg >> 8));
 	}
-	it8712f_exit_conf();
 }
 
 void main(unsigned long bist)
@@ -126,7 +126,7 @@ void main(unsigned long bist)
 	 * Note: Must do this AFTER the early_setup! It is counting on some
 	 * early MSR setup for CS5536.
 	 */
-	it8712f_enable_serial(0, CONFIG_TTYS0_BASE); // Does not use its 1st parameter
+	ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	mb_gpio_init();
 	console_init();
 
diff --git a/src/mainboard/lippert/literunner-lx/romstage.c b/src/mainboard/lippert/literunner-lx/romstage.c
index 6edcf373dd..174620a8ac 100644
--- a/src/mainboard/lippert/literunner-lx/romstage.c
+++ b/src/mainboard/lippert/literunner-lx/romstage.c
@@ -35,9 +35,13 @@
 #include "southbridge/amd/cs5536/cs5536.h"
 #include "southbridge/amd/cs5536/early_smbus.c"
 #include "southbridge/amd/cs5536/early_setup.c"
-#include "superio/ite/it8712f/early_serial.c"
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8712f/it8712f.h>
 #include "northbridge/amd/lx/raminit.h"
 
+#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
+#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO)
+
 /* Bit0 enables Spread Spectrum, bit1 makes on-board CF slot act as IDE slave. */
 #if CONFIG_ONBOARD_IDE_SLAVE
 	#define SMC_CONFIG	0x03
@@ -118,7 +122,6 @@ static int smc_send_config(unsigned char config_data)
 #include "cpu/amd/geode_lx/msrinit.c"
 
 static const u16 sio_init_table[] = { // hi=data, lo=index
-	0x0707,		// select LDN 7 (GPIO, SPI, watchdog, ...)
 	0x072C,		// VIN6 enabled, FAN4/5 disabled, VIN7,VIN3 internal
 	0x1423,		// don't delay PoWeROK1/2
 	0x9072,		// watchdog triggers PWROK, counts seconds
@@ -143,13 +146,10 @@ static void mb_gpio_init(void)
 	int i;
 
 	/* Init Super I/O WDT, GPIOs. Done early, WDT init may trigger reset! */
-	it8712f_enter_conf();
 	for (i = 0; i < ARRAY_SIZE(sio_init_table); i++) {
-		u16 val = sio_init_table[i];
-		outb((u8)val, SIO_INDEX);
-		outb(val >> 8, SIO_DATA);
+		u16 reg = sio_init_table[i];
+		ite_reg_write(GPIO_DEV, (u8) reg, (reg >> 8));
 	}
-	it8712f_exit_conf();
 }
 
 void main(unsigned long bist)
@@ -169,7 +169,7 @@ void main(unsigned long bist)
 	 * Note: Must do this AFTER the early_setup! It is counting on some
 	 * early MSR setup for CS5536.
 	 */
-	it8712f_enable_serial(0, CONFIG_TTYS0_BASE); // Does not use its 1st parameter
+	ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	mb_gpio_init();
 	console_init();
 
diff --git a/src/mainboard/lippert/roadrunner-lx/romstage.c b/src/mainboard/lippert/roadrunner-lx/romstage.c
index 68dcfc0ff1..2642373efd 100644
--- a/src/mainboard/lippert/roadrunner-lx/romstage.c
+++ b/src/mainboard/lippert/roadrunner-lx/romstage.c
@@ -35,9 +35,13 @@
 #include <spd.h>
 #include "southbridge/amd/cs5536/early_smbus.c"
 #include "southbridge/amd/cs5536/early_setup.c"
-#include "superio/ite/it8712f/early_serial.c"
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8712f/it8712f.h>
 #include "northbridge/amd/lx/raminit.h"
 
+#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
+#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO)
+
 int spd_read_byte(unsigned int device, unsigned int address)
 {
 	if (device != DIMM0)
@@ -53,7 +57,6 @@ int spd_read_byte(unsigned int device, unsigned int address)
 #include "cpu/amd/geode_lx/msrinit.c"
 
 static const u16 sio_init_table[] = {	// hi=data, lo=index
-	0x0707,		// select LDN 7 (GPIO, SPI, watchdog, ...)
 	0x1E2C,		// disable ATXPG; VIN6,FAN4/5,VIN3 enabled, VIN7 internal
 	0x1423,		// don't delay PoWeROK1/2 - triggers 2nd reset
 	0x9072,		// watchdog triggers PWROK, counts seconds
@@ -76,13 +79,10 @@ static void mb_gpio_init(void)
 	int i;
 
 	/* Init Super I/O WDT, GPIOs. Done early, WDT init may trigger reset! */
-	it8712f_enter_conf();
 	for (i = 0; i < ARRAY_SIZE(sio_init_table); i++) {
-		u16 val = sio_init_table[i];
-		outb((u8)val, SIO_INDEX);
-		outb(val >> 8, SIO_DATA);
+		u16 reg = sio_init_table[i];
+		ite_reg_write(GPIO_DEV, (u8) reg, (reg >> 8));
 	}
-	it8712f_exit_conf();
 }
 
 void main(unsigned long bist)
@@ -101,7 +101,7 @@ void main(unsigned long bist)
 	 * Note: must do this AFTER the early_setup! It is counting on some
 	 * early MSR setup for CS5536.
 	 */
-	it8712f_enable_serial(0, CONFIG_TTYS0_BASE); // Does not use its 1st parameter
+	ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	mb_gpio_init();
 	console_init();
 
diff --git a/src/mainboard/lippert/spacerunner-lx/romstage.c b/src/mainboard/lippert/spacerunner-lx/romstage.c
index 59bd618eb1..9d5539e2bb 100644
--- a/src/mainboard/lippert/spacerunner-lx/romstage.c
+++ b/src/mainboard/lippert/spacerunner-lx/romstage.c
@@ -35,9 +35,13 @@
 #include "southbridge/amd/cs5536/cs5536.h"
 #include "southbridge/amd/cs5536/early_smbus.c"
 #include "southbridge/amd/cs5536/early_setup.c"
-#include "superio/ite/it8712f/early_serial.c"
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8712f/it8712f.h>
 #include "northbridge/amd/lx/raminit.h"
 
+#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
+#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO)
+
 /* Bit0 enables Spread Spectrum, bit1 makes on-board SSD act as IDE slave. */
 #if CONFIG_ONBOARD_IDE_SLAVE
 	#define SMC_CONFIG	0x03
@@ -118,7 +122,6 @@ static int smc_send_config(unsigned char config_data)
 #include "cpu/amd/geode_lx/msrinit.c"
 
 static const u16 sio_init_table[] = { // hi=data, lo=index
-	0x0707,		// select LDN 7 (GPIO, SPI, watchdog, ...)
 	0x072C,		// VIN6 enabled, FAN4/5 disabled, VIN7,VIN3 internal
 	0x1423,		// don't delay PoWeROK1/2
 	0x9072,		// watchdog triggers PWROK, counts seconds
@@ -140,13 +143,10 @@ static void mb_gpio_init(void)
 	int i;
 
 	/* Init Super I/O WDT, GPIOs. Done early, WDT init may trigger reset! */
-	it8712f_enter_conf();
 	for (i = 0; i < ARRAY_SIZE(sio_init_table); i++) {
-		u16 val = sio_init_table[i];
-		outb((u8)val, SIO_INDEX);
-		outb(val >> 8, SIO_DATA);
+		u16 reg = sio_init_table[i];
+		ite_reg_write(GPIO_DEV, (u8) reg, (reg >> 8));
 	}
-	it8712f_exit_conf();
 }
 
 void main(unsigned long bist)
@@ -166,7 +166,7 @@ void main(unsigned long bist)
 	 * Note: Must do this AFTER the early_setup! It is counting on some
 	 * early MSR setup for CS5536.
 	 */
-	it8712f_enable_serial(0, CONFIG_TTYS0_BASE); // Does not use its 1st parameter
+	ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	mb_gpio_init();
 	console_init();
 
diff --git a/src/mainboard/siemens/sitemp_g1p1/romstage.c b/src/mainboard/siemens/sitemp_g1p1/romstage.c
index 6ae4989d15..b8af3548c7 100644
--- a/src/mainboard/siemens/sitemp_g1p1/romstage.c
+++ b/src/mainboard/siemens/sitemp_g1p1/romstage.c
@@ -35,7 +35,8 @@
 
 #include "cpu/x86/lapic.h"
 #include "northbridge/amd/amdk8/reset_test.c"
-#include "superio/ite/it8712f/early_serial.c"
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8712f/it8712f.h>
 
 #include "cpu/x86/bist.h"
 
@@ -45,6 +46,8 @@
 #include "southbridge/amd/sb600/early_setup.c"
 #include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */
 
+#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
+
 /* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/
 static void memreset(int controllers, const struct mem_controller *ctrl)
 {
@@ -103,8 +106,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 #if defined(DUMP_CMOS_RAM) && (DUMP_CMOS_RAM == 0)
 	check_cmos();  // rebooting in case of corrupted cmos !!!!!
 #endif
-	/* it8712f_enable_serial does not use its 1st parameter. */
-	it8712f_enable_serial(0, CONFIG_TTYS0_BASE);
+	ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	it8712f_kill_watchdog();
 
 	console_init();
diff --git a/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c b/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c
index 632a3117a5..551c060944 100644
--- a/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c
+++ b/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c
@@ -30,8 +30,7 @@
 #include "drivers/pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "cpu/x86/bist.h"
-void it8671f_48mhz_clkin(void);
-#include "superio/ite/it8671f/early_serial.c"
+#include <superio/ite/it8671f/it8671f.h>
 #include <lib.h>
 
 #define SERIAL_DEV PNP_DEV(0x370, IT8671F_SP1)
diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c
index e6483c0e21..35351b1266 100644
--- a/src/mainboard/technexion/tim5690/romstage.c
+++ b/src/mainboard/technexion/tim5690/romstage.c
@@ -32,12 +32,15 @@
 #include "cpu/x86/lapic.h"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
-#include "superio/ite/it8712f/early_serial.c"
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8712f/it8712f.h>
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 #include "southbridge/amd/rs690/early_setup.c"
 #include "southbridge/amd/sb600/early_setup.c"
 
+#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
+
 static void memreset(int controllers, const struct mem_controller *ctrl) { }
 static void activate_spd_rom(const struct mem_controller *ctrl) { }
 
@@ -85,8 +88,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	enable_rs690_dev8();
 	sb600_lpc_init();
 
-	/* it8712f_enable_serial does not use its 1st parameter. */
-	it8712f_enable_serial(0, CONFIG_TTYS0_BASE);
+	ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	it8712f_kill_watchdog();
 
 	console_init();
diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c
index 2f3ad71562..7455df2327 100644
--- a/src/mainboard/technexion/tim8690/romstage.c
+++ b/src/mainboard/technexion/tim8690/romstage.c
@@ -32,12 +32,15 @@
 #include "cpu/x86/lapic.h"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
-#include "superio/ite/it8712f/early_serial.c"
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8712f/it8712f.h>
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 #include "southbridge/amd/rs690/early_setup.c"
 #include "southbridge/amd/sb600/early_setup.c"
 
+#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
+
 static void memreset(int controllers, const struct mem_controller *ctrl) { }
 static void activate_spd_rom(const struct mem_controller *ctrl) { }
 
@@ -80,8 +83,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	enable_rs690_dev8();
 	sb600_lpc_init();
 
-	/* it8712f_enable_serial does not use its 1st parameter. */
-	it8712f_enable_serial(0, CONFIG_TTYS0_BASE);
+	ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	it8712f_kill_watchdog();
 
 	console_init();
diff --git a/src/mainboard/via/pc2500e/romstage.c b/src/mainboard/via/pc2500e/romstage.c
index e374cf93b7..b2703506a2 100644
--- a/src/mainboard/via/pc2500e/romstage.c
+++ b/src/mainboard/via/pc2500e/romstage.c
@@ -32,6 +32,7 @@
 #include "drivers/pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "southbridge/via/vt8237r/early_smbus.c"
+#include <superio/ite/common/ite.h>
 #include <superio/ite/it8716f/it8716f.h>
 #include <spd.h>
 
@@ -59,7 +60,7 @@ void main(unsigned long bist)
 	/* Enable multifunction for northbridge. */
 	pci_write_config8(ctrl.d0f0, 0x4f, 0x01);
 
-	it8716f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	console_init();
 	enable_smbus();
 	smbus_fixup(&ctrl);
diff --git a/src/superio/ite/Kconfig b/src/superio/ite/Kconfig
index 4c0f927022..8a5378df3a 100644
--- a/src/superio/ite/Kconfig
+++ b/src/superio/ite/Kconfig
@@ -2,6 +2,7 @@
 ## This file is part of the coreboot project.
 ##
 ## Copyright (C) 2009 Ronald G. Minnich
+## Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
 ##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by
@@ -17,24 +18,45 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 ##
 
+# Generic ITE romstage driver - Just enough UART initialisation code for
+# romstage.
+config SUPERIO_ITE_COMMON_ROMSTAGE
+	bool
 
 config SUPERIO_ITE_IT8661F
 	bool
+	select SUPERIO_ITE_COMMON_ROMSTAGE
+
 config SUPERIO_ITE_IT8671F
 	bool
+	select SUPERIO_ITE_COMMON_ROMSTAGE
+
 config SUPERIO_ITE_IT8712F
 	bool
+	select SUPERIO_ITE_COMMON_ROMSTAGE
+
 config SUPERIO_ITE_IT8716F
 	bool
+	select SUPERIO_ITE_COMMON_ROMSTAGE
+
 config SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL
 	bool
 	depends on SUPERIO_ITE_IT8716F
 	default n
+	select SUPERIO_ITE_COMMON_ROMSTAGE
+
 config SUPERIO_ITE_IT8718F
 	bool
+	select SUPERIO_ITE_COMMON_ROMSTAGE
+
 config SUPERIO_ITE_IT8721F
 	bool
+	select SUPERIO_ITE_COMMON_ROMSTAGE
+
 config SUPERIO_ITE_IT8728F
 	bool
+	select SUPERIO_ITE_COMMON_ROMSTAGE
+
 config SUPERIO_ITE_IT8772F
 	bool
+	select SUPERIO_ITE_COMMON_ROMSTAGE
diff --git a/src/superio/ite/Makefile.inc b/src/superio/ite/Makefile.inc
index 2b715211d9..7e1c81b707 100644
--- a/src/superio/ite/Makefile.inc
+++ b/src/superio/ite/Makefile.inc
@@ -17,6 +17,9 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 ##
 
+## include generic ite pre-ram stage driver
+romstage-$(CONFIG_SUPERIO_ITE_COMMON_ROMSTAGE) += common/early_serial.c
+
 subdirs-y += it8661f
 subdirs-y += it8671f
 subdirs-y += it8712f
diff --git a/src/superio/ite/it8721f/early_serial.c b/src/superio/ite/common/early_serial.c
index df662223dc..35fb59d64a 100644
--- a/src/superio/ite/it8721f/early_serial.c
+++ b/src/superio/ite/common/early_serial.c
@@ -1,8 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
- * Copyright (C) 2011 QingPei Wang <wangqingpei@gmail.com>
+ * Copyright (C) 2013 Damien Zammit <damien@zamaudio.com>
  * Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
  *
  * This program is free software; you can redistribute it and/or modify
@@ -23,21 +22,23 @@
 #include <arch/io.h>
 #include <device/pnp.h>
 #include <stdint.h>
-#include "it8721f.h"
+#include "ite.h"
 
 /* Global configuration registers. */
-#define IT8721F_CONFIG_REG_CC        0x02 /* Configure Control (write-only). */
-#define IT8721F_CONFIG_REG_LDN       0x07 /* Logical Device Number. */
-#define IT8721F_CONFIG_REG_CLOCKSEL  0x23 /* Clock Selection. */
-#define IT8721F_CONFIG_REG_SWSUSP    0x24 /* Software Suspend, Flash I/F. */
+#define ITE_CONFIG_REG_CC        0x02 /* Configure Control (write-only). */
+#define ITE_CONFIG_REG_LDN       0x07 /* Logical Device Number. */
+#define ITE_CONFIG_REG_CLOCKSEL  0x23 /* Clock Selection. */
+#define ITE_CONFIG_REG_SWSUSP    0x24 /* Software Suspend, Flash I/F. */
 
-static void it8721f_sio_write(device_t dev, u8 index, u8 value)
+/* Helper procedure */
+static void ite_sio_write(device_t dev, u8 reg, u8 value)
 {
 	pnp_set_logical_device(dev);
-	pnp_write_config(dev, index, value);
+	pnp_write_config(dev, reg, value);
 }
 
-static void it8721f_enter_conf(device_t dev)
+/* Enable configuration */
+static void pnp_enter_conf_state(device_t dev)
 {
 	u16 port = dev >> 8;
 
@@ -47,39 +48,39 @@ static void it8721f_enter_conf(device_t dev)
 	outb((port == 0x4e) ? 0xaa : 0x55, port);
 }
 
-static void it8721f_exit_conf(device_t dev)
+/* Disable configuration */
+static void pnp_exit_conf_state(device_t dev)
 {
-	it8721f_sio_write(dev, IT8721F_CONFIG_REG_CC, 0x02);
+	ite_sio_write(dev, ITE_CONFIG_REG_CC, 0x02);
 }
 
-static void it8721f_reg_write(device_t dev, u8 index, u8 value)
+void ite_reg_write(device_t dev, u8 reg, u8 value)
 {
-	it8721f_enter_conf(dev);
-	it8721f_sio_write(dev, index, value);
-	it8721f_exit_conf(dev);
+	pnp_enter_conf_state(dev);
+	ite_sio_write(dev, reg, value);
+	pnp_exit_conf_state(dev);
 }
 
 
 /*
  * in romstage.c
- * #define CLKIN_DEV PNP_DEV(0x2e, IT8721F_GPIO)
+ * #define CLKIN_DEV PNP_DEV(0x2e, ITE_GPIO)
  * and pass: CLKIN_DEV
- * IT8721F_UART_CLK_PREDIVIDE_24
- * IT8721F_UART_CLK_PREDIVIDE_48 (default)
+ * ITE_UART_CLK_PREDIVIDE_24
+ * ITE_UART_CLK_PREDIVIDE_48 (default)
  */
-void it8721f_conf_clkin(device_t dev, u8 predivide)
+void ite_conf_clkin(device_t dev, u8 predivide)
 {
-	it8721f_reg_write(dev, IT8721F_CONFIG_REG_CLOCKSEL, (0x1 & predivide));
+	ite_reg_write(dev, ITE_CONFIG_REG_CLOCKSEL, (0x1 & predivide));
 }
 
-
-/* Enable the serial port(s). */
-void it8721f_enable_serial(device_t dev, u16 iobase)
+/* Bring up early serial debugging output before the RAM is initialized. */
+void ite_enable_serial(device_t dev, u16 iobase)
 {
-	it8721f_enter_conf(dev);
+	pnp_enter_conf_state(dev);
 	pnp_set_logical_device(dev);
 	pnp_set_enable(dev, 0);
 	pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
 	pnp_set_enable(dev, 1);
-	it8721f_exit_conf(dev);
+	pnp_exit_conf_state(dev);
 }
diff --git a/src/superio/ite/common/ite.h b/src/superio/ite/common/ite.h
new file mode 100644
index 0000000000..f21381de6f
--- /dev/null
+++ b/src/superio/ite/common/ite.h
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef SUPERIO_ITE_COMMON_ROMSTAGE_H
+#define SUPERIO_ITE_COMMON_ROMSTAGE_H
+
+#include <arch/io.h>
+#include <stdint.h>
+
+#define ITE_UART_CLK_PREDIVIDE_48 0x00 /* default */
+#define ITE_UART_CLK_PREDIVIDE_24 0x01
+
+void ite_conf_clkin(device_t dev, u8 predivide);
+void ite_enable_serial(device_t dev, u16 iobase);
+
+/* Some boards need to init wdt+gpio's very early */
+void ite_reg_write(device_t dev, u8 reg, u8 value);
+
+#endif /* SUPERIO_ITE_COMMON_ROMSTAGE_H */
diff --git a/src/superio/ite/it8671f/Makefile.inc b/src/superio/ite/it8671f/Makefile.inc
index bb370ae179..a9a40085be 100644
--- a/src/superio/ite/it8671f/Makefile.inc
+++ b/src/superio/ite/it8671f/Makefile.inc
@@ -18,5 +18,5 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 ##
 
+romstage-$(CONFIG_SUPERIO_ITE_IT8671F) += early_serial.c
 ramstage-$(CONFIG_SUPERIO_ITE_IT8671F) += superio.c
-
diff --git a/src/superio/ite/it8671f/early_serial.c b/src/superio/ite/it8671f/early_serial.c
index c2ba6e02a1..9f35b8ad8e 100644
--- a/src/superio/ite/it8671f/early_serial.c
+++ b/src/superio/ite/it8671f/early_serial.c
@@ -19,6 +19,8 @@
  */
 
 #include <arch/io.h>
+#include <device/pnp.h>
+#include <stdint.h>
 #include "it8671f.h"
 
 /* The base address is 0x3f0, 0x3bd, or 0x370, depending on config bytes. */
@@ -87,7 +89,7 @@ void it8671f_48mhz_clkin(void)
 }
 
 /* Enable the serial port(s). */
-static void it8671f_enable_serial(device_t dev, u16 iobase)
+void it8671f_enable_serial(device_t dev, u16 iobase)
 {
 	it8671f_enter_conf();
 
diff --git a/src/superio/ite/it8671f/it8671f.h b/src/superio/ite/it8671f/it8671f.h
index 52669f4ba5..c3865ff74e 100644
--- a/src/superio/ite/it8671f/it8671f.h
+++ b/src/superio/ite/it8671f/it8671f.h
@@ -18,8 +18,11 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-#ifndef SUPERIO_ITE_IT8671F_IT8671F_H
-#define SUPERIO_ITE_IT8671F_IT8671F_H
+#ifndef SUPERIO_ITE_IT8671F_H
+#define SUPERIO_ITE_IT8671F_H
+
+#include <arch/io.h>
+#include <stdint.h>
 
 /* Datasheet: Not available online, got it from ITE per request. */
 
@@ -30,4 +33,7 @@
 #define IT8671F_KBCK 0x05 /* PS/2 keyboard */
 #define IT8671F_KBCM 0x06 /* PS/2 mouse */
 
-#endif
+void it8671f_48mhz_clkin(void);
+void it8671f_enable_serial(device_t dev, u16 iobase);
+
+#endif /* SUPERIO_ITE_IT8671F__H */
diff --git a/src/superio/ite/it8712f/Makefile.inc b/src/superio/ite/it8712f/Makefile.inc
index 3c8a5125e9..ce756453b5 100644
--- a/src/superio/ite/it8712f/Makefile.inc
+++ b/src/superio/ite/it8712f/Makefile.inc
@@ -18,5 +18,5 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 ##
 
+romstage-$(CONFIG_SUPERIO_ITE_IT8712F) += early_serial.c
 ramstage-$(CONFIG_SUPERIO_ITE_IT8712F) += superio.c
-
diff --git a/src/superio/ite/it8712f/early_serial.c b/src/superio/ite/it8712f/early_serial.c
index 51564fce04..d678f3faba 100644
--- a/src/superio/ite/it8712f/early_serial.c
+++ b/src/superio/ite/it8712f/early_serial.c
@@ -19,6 +19,8 @@
  */
 
 #include <arch/io.h>
+#include <device/pnp.h>
+#include <stdint.h>
 #include "it8712f.h"
 
 /* The base address is 0x2e or 0x4e, depending on config bytes. */
@@ -30,7 +32,6 @@
 #define IT8712F_CONFIG_REG_CC        0x02 /* Configure Control (write-only). */
 #define IT8712F_CONFIG_REG_LDN       0x07 /* Logical Device Number. */
 #define IT8712F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */
-#define IT8712F_CONFIG_REG_CLOCKSEL  0x23 /* Clock Selection. */
 #define IT8712F_CONFIG_REG_SWSUSP    0x24 /* Software Suspend, Flash I/F. */
 #define IT8712F_CONFIG_REG_MFC       0x2a /* Multi-function control */
 #define IT8712F_CONFIG_REG_WATCHDOG  0x72 /* Watchdog control. */
@@ -58,14 +59,6 @@ static void it8712f_exit_conf(void)
 	it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CC, 0x02);
 }
 
-/* Select 24MHz CLKIN (48MHz is the default). */
-void it8712f_24mhz_clkin(void)
-{
-	it8712f_enter_conf();
-	it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CLOCKSEL, 0x1);
-	it8712f_exit_conf();
-}
-
 /*
  * We need to set enable 3VSBSW#, this was documented only in IT8712F_V0.9.2!
  *
@@ -88,30 +81,3 @@ void it8712f_kill_watchdog(void)
 	it8712f_sio_write(IT8712F_GPIO, IT8712F_CONFIG_REG_WATCHDOG, 0x00);
 	it8712f_exit_conf();
 }
-
-/* Enable the serial port(s). */
-void it8712f_enable_serial(device_t dev, u16 iobase)
-{
-	/* (1) Enter the configuration state (MB PnP mode). */
-	it8712f_enter_conf();
-
-	/* (2) Modify the data of configuration registers. */
-
-	/*
-	 * Select the chip to configure (if there's more than one).
-	 * Set bit 7 to select JP3=1, clear bit 7 to select JP3=0.
-	 * If this register is not written, both chips are configured.
-	 */
-
-	/* it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CONFIGSEL, 0x00); */
-
-	/* Enable serial port(s). */
-	it8712f_sio_write(IT8712F_SP1, 0x30, 0x1); /* Serial port 1 */
-	it8712f_sio_write(IT8712F_SP2, 0x30, 0x1); /* Serial port 2 */
-
-	/* Clear software suspend mode (clear bit 0). TODO: Needed? */
-	/* it8712f_sio_write(0x00, IT8712F_CONFIG_REG_SWSUSP, 0x00); */
-
-	/* (3) Exit the configuration state (MB PnP mode). */
-	it8712f_exit_conf();
-}
diff --git a/src/superio/ite/it8712f/it8712f.h b/src/superio/ite/it8712f/it8712f.h
index 5ec6188eae..b40e473c10 100644
--- a/src/superio/ite/it8712f/it8712f.h
+++ b/src/superio/ite/it8712f/it8712f.h
@@ -18,8 +18,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-#ifndef SUPERIO_ITE_IT8712F_IT8712F_H
-#define SUPERIO_ITE_IT8712F_IT8712F_H
+#ifndef SUPERIO_ITE_IT8712F_H
+#define SUPERIO_ITE_IT8712F_H
 
 /* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8712_2.asp */
 
@@ -36,7 +36,6 @@
 #define IT8712F_IR   0x0a /* Consumer IR */
 
 void it8712f_kill_watchdog(void);
-void it8712f_enable_serial(device_t dev, u16 iobase);
-void it8712f_24mhz_clkin(void);
 void it8712f_enable_3vsbsw(void);
-#endif
+
+#endif /* SUPERIO_ITE_IT8712F_H */
diff --git a/src/superio/ite/it8716f/Makefile.inc b/src/superio/ite/it8716f/Makefile.inc
index 6b3c0cec79..a11c2ab6ef 100644
--- a/src/superio/ite/it8716f/Makefile.inc
+++ b/src/superio/ite/it8716f/Makefile.inc
@@ -18,5 +18,4 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 ##
 
-romstage-$(CONFIG_SUPERIO_ITE_IT8716F) += early_serial.c
 ramstage-$(CONFIG_SUPERIO_ITE_IT8716F) += superio.c
diff --git a/src/superio/ite/it8716f/early_serial.c b/src/superio/ite/it8716f/early_serial.c
deleted file mode 100644
index 2085a8fee2..0000000000
--- a/src/superio/ite/it8716f/early_serial.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
- * Copyright (C) 2007 AMD Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
- * Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include <device/pnp.h>
-#include "it8716f.h"
-
-/* Global configuration registers. */
-#define IT8716F_CONFIG_REG_CC        0x02 /* Configure Control (write-only). */
-#define IT8716F_CONFIG_REG_LDN       0x07 /* Logical Device Number. */
-#define IT8716F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */
-#define IT8716F_CONFIG_REG_CLOCKSEL  0x23 /* Clock Selection. */
-#define IT8716F_CONFIG_REG_SWSUSP    0x24 /* Software Suspend, Flash I/F. */
-
-static void it8716f_enter_conf(device_t dev)
-{
-	u16 port = dev >> 8;
-
-	outb(0x87, port);
-	outb(0x01, port);
-	outb(0x55, port);
-	outb((port == 0x4e) ? 0xaa : 0x55, port);
-}
-
-static void it8716f_exit_conf(device_t dev)
-{
-	pnp_write_config(dev, IT8716F_CONFIG_REG_CC, 0x02);
-}
-
-static void it8716f_reg_write(device_t dev, u8 index, u8 value)
-{
-	it8716f_enter_conf(dev);
-	pnp_write_config(dev, index, value);
-	it8716f_exit_conf(dev);
-}
-
-
-/*
- * in romstage.c
- * #define CLKIN_DEV PNP_DEV(0x2e, IT8716F_GPIO)
- * and pass: CLKIN_DEV
- * IT8716F_UART_CLK_PREDIVIDE_24
- * IT8716F_UART_CLK_PREDIVIDE_48 (default)
- */
-void it8716f_conf_clkin(device_t dev, u8 predivide)
-{
-	it8716f_reg_write(dev, IT8716F_CONFIG_REG_CLOCKSEL, (0x1 & predivide));
-}
-
-
-/* Enable the serial port(s). */
-void it8716f_enable_serial(device_t dev, u16 iobase)
-{
-	it8716f_enter_conf(dev);
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 0);
-	pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
-	pnp_set_enable(dev, 1);
-	it8716f_exit_conf(dev);
-}
diff --git a/src/superio/ite/it8716f/it8716f.h b/src/superio/ite/it8716f/it8716f.h
index 37b8b654f9..bbf57081e7 100644
--- a/src/superio/ite/it8716f/it8716f.h
+++ b/src/superio/ite/it8716f/it8716f.h
@@ -21,7 +21,6 @@
 #ifndef SUPERIO_ITE_IT8716F_H
 #define SUPERIO_ITE_IT8716F_H
 
-#include <device/pnp.h>
 #include <stdint.h>
 
 /* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8716_2.asp */
@@ -39,12 +38,6 @@
 #define IT8716F_GAME 0x09 /* GAME port */
 #define IT8716F_IR   0x0a /* Consumer IR */
 
-#define IT8716F_UART_CLK_PREDIVIDE_48 0x00 /* default */
-#define IT8716F_UART_CLK_PREDIVIDE_24 0x01
-
-void it8716f_conf_clkin(device_t dev, u8 predivide);
-void it8716f_enable_serial(device_t dev, u16 iobase);
-
 #if CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL
 /* Provided by mainboard, called by IT8716F superio.c. */
 void init_ec(u16 base);
diff --git a/src/superio/ite/it8718f/Makefile.inc b/src/superio/ite/it8718f/Makefile.inc
index c433e3c572..14e28223a1 100644
--- a/src/superio/ite/it8718f/Makefile.inc
+++ b/src/superio/ite/it8718f/Makefile.inc
@@ -18,5 +18,5 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 ##
 
+romstage-$(CONFIG_SUPERIO_ITE_IT8718F) += early_serial.c
 ramstage-$(CONFIG_SUPERIO_ITE_IT8718F) += superio.c
-
diff --git a/src/superio/ite/it8718f/early_serial.c b/src/superio/ite/it8718f/early_serial.c
index 308b67cd40..deef84043f 100644
--- a/src/superio/ite/it8718f/early_serial.c
+++ b/src/superio/ite/it8718f/early_serial.c
@@ -30,7 +30,6 @@
 #define IT8718F_CONFIG_REG_CC        0x02 /* Configure Control (write-only). */
 #define IT8718F_CONFIG_REG_LDN       0x07 /* Logical Device Number. */
 #define IT8718F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */
-#define IT8718F_CONFIG_REG_CLOCKSEL  0x23 /* Clock Selection. */
 #define IT8718F_CONFIG_REG_SWSUSP    0x24 /* Software Suspend, Flash I/F. */
 
 static void it8718f_sio_write(u8 ldn, u8 index, u8 value)
@@ -56,13 +55,6 @@ static void it8718f_exit_conf(void)
 	it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CC, 0x02);
 }
 
-/* Select 24MHz CLKIN (48MHz default). */
-void it8718f_24mhz_clkin(void)
-{
-	it8718f_enter_conf();
-	it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CLOCKSEL, 0x1);
-	it8718f_exit_conf();
-}
 
 /*
  * GIGABYTE uses a special Super I/O register to protect its Dual BIOS
@@ -75,30 +67,3 @@ void it8718f_disable_reboot(void)
 	it8718f_sio_write(IT8718F_GPIO, 0xEF, 0x7E);
 	it8718f_exit_conf();
 }
-
-/* Enable the serial port(s). */
-void it8718f_enable_serial(device_t dev, u16 iobase)
-{
-	/* (1) Enter the configuration state (MB PnP mode). */
-	it8718f_enter_conf();
-
-	/* (2) Modify the data of configuration registers. */
-
-	/*
-	 * Select the chip to configure (if there's more than one).
-	 * Set bit 7 to select JP3=1, clear bit 7 to select JP3=0.
-	 * If this register is not written, both chips are configured.
-	 */
-
-	/* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CONFIGSEL, 0x00); */
-
-	/* Enable serial port(s). */
-	it8718f_sio_write(IT8718F_SP1, 0x30, 0x1); /* Serial port 1 */
-	it8718f_sio_write(IT8718F_SP2, 0x30, 0x1); /* Serial port 2 */
-
-	/* Clear software suspend mode (clear bit 0). TODO: Needed? */
-	/* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_SWSUSP, 0x00); */
-
-	/* (3) Exit the configuration state (MB PnP mode). */
-	it8718f_exit_conf();
-}
diff --git a/src/superio/ite/it8718f/it8718f.h b/src/superio/ite/it8718f/it8718f.h
index 527d1c2409..018f08a642 100644
--- a/src/superio/ite/it8718f/it8718f.h
+++ b/src/superio/ite/it8718f/it8718f.h
@@ -18,8 +18,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-#ifndef SUPERIO_ITE_IT8718F_IT8718F_H
-#define SUPERIO_ITE_IT8718F_IT8718F_H
+#ifndef SUPERIO_ITE_IT8718F_H
+#define SUPERIO_ITE_IT8718F_H
 
 /* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8718_2.asp */
 
@@ -34,9 +34,7 @@
 #define IT8718F_IR   0x0a /* Consumer IR */
 
 #if defined(__PRE_RAM__)
-void it8718f_24mhz_clkin(void);
 void it8718f_disable_reboot(void);
-void it8718f_enable_serial(device_t dev, u16 iobase);
 #endif
 
-#endif
+#endif /* SUPERIO_ITE_IT8718F_H */
diff --git a/src/superio/ite/it8721f/Makefile.inc b/src/superio/ite/it8721f/Makefile.inc
index ef616f4460..4b1aa96b63 100644
--- a/src/superio/ite/it8721f/Makefile.inc
+++ b/src/superio/ite/it8721f/Makefile.inc
@@ -18,5 +18,4 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 ##
 
-romstage-$(CONFIG_SUPERIO_ITE_IT8721F) += early_serial.c
 ramstage-$(CONFIG_SUPERIO_ITE_IT8721F) += superio.c
diff --git a/src/superio/ite/it8721f/it8721f.h b/src/superio/ite/it8721f/it8721f.h
index 9d5a528295..ce794cfdce 100644
--- a/src/superio/ite/it8721f/it8721f.h
+++ b/src/superio/ite/it8721f/it8721f.h
@@ -36,10 +36,4 @@
 #define IT8721F_GPIO 0x07 /* GPIO */
 #define IT8721F_IR   0x0a /* Consumer IR */
 
-#define IT8721F_UART_CLK_PREDIVIDE_48 0x00 /* default */
-#define IT8721F_UART_CLK_PREDIVIDE_24 0x01
-
-void it8721f_conf_clkin(device_t dev, u8 predivide);
-void it8721f_enable_serial(device_t dev, u16 iobase);
-
 #endif /* SUPERIO_ITE_IT8721F_H */
diff --git a/src/superio/ite/it8728f/Makefile.inc b/src/superio/ite/it8728f/Makefile.inc
index a146db8053..00cceebee9 100644
--- a/src/superio/ite/it8728f/Makefile.inc
+++ b/src/superio/ite/it8728f/Makefile.inc
@@ -18,6 +18,5 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 ##
 
-romstage-$(CONFIG_SUPERIO_ITE_IT8728F) += early_serial.c
 ramstage-$(CONFIG_SUPERIO_ITE_IT8728F) += it8728f_hwm.c
 ramstage-$(CONFIG_SUPERIO_ITE_IT8728F) += superio.c
diff --git a/src/superio/ite/it8728f/early_serial.c b/src/superio/ite/it8728f/early_serial.c
deleted file mode 100644
index c2632eff34..0000000000
--- a/src/superio/ite/it8728f/early_serial.c
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
- * Copyright (C) 2013 Damien Zammit <damien@zamaudio.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include <device/pnp.h>
-#include "it8728f.h"
-
-/* Superio raw commands */
-static void it8728f_sio_write(device_t dev, u8 index, u8 value)
-{
-	pnp_set_logical_device(dev);
-	pnp_write_config(dev, index, value);
-}
-
-static void it8728f_enter_conf(device_t dev)
-{
-	u16 port = dev >> 8;
-
-	outb(0x87, port);
-	outb(0x01, port);
-	outb(0x55, port);
-	outb((port == 0x4e) ? 0xaa : 0x55, port);
-}
-
-static void it8728f_exit_conf(device_t dev)
-{
-	it8728f_sio_write(dev, IT8728F_CONFIG_REG_CC, 0x02);
-}
-
-/* Superio low level commands */
-void it8728f_reg_write(device_t dev, u8 index, u8 value)
-{
-	it8728f_enter_conf(dev);
-	it8728f_sio_write(dev, index, value);
-	it8728f_exit_conf(dev);
-}
-
-void it8728f_24mhz_clkin(device_t dev)
-{
-	it8728f_reg_write(dev, IT8728F_CONFIG_REG_CLOCKSEL, 0x1);
-}
-
-void it8728f_enable_serial(device_t dev, u16 iobase)
-{
-	/* (1) Enter the configuration state (MB PnP mode). */
-	it8728f_enter_conf(dev);
-
-	/* (2) Modify the data of configuration registers. */
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 0);
-	pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
-	pnp_set_enable(dev, 1);
-
-	/* (3) Exit the configuration state (MB PnP mode). */
-	it8728f_exit_conf(dev);
-}
diff --git a/src/superio/ite/it8728f/it8728f.h b/src/superio/ite/it8728f/it8728f.h
index 55bdf697bc..8a7e8b2e71 100644
--- a/src/superio/ite/it8728f/it8728f.h
+++ b/src/superio/ite/it8728f/it8728f.h
@@ -39,16 +39,4 @@
 #define IT8728F_CONFIG_REG_CLOCKSEL  0x23 /* Clock Selection. */
 #define IT8728F_CONFIG_REG_SWSUSP    0x24 /* Software Suspend, Flash I/F. 'Special register' */
 
-/*
- * Superio low level commands
- * Pass dev = PNP_DEV(superiobase, LDN)
- */
-void it8728f_reg_write(device_t dev, u8 index, u8 value);
-
-/* Select 24MHz CLKIN (48MHz default). */
-void it8728f_24mhz_clkin(device_t dev);
-
-/* Enable the serial port(s). */
-void it8728f_enable_serial(device_t dev, u16 iobase);
-
 #endif /* SUPERIO_ITE_IT8728F_H */