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| author | Andrey Petrov <andrey.petrov@intel.com> | 2016-11-18 14:57:51 -0800 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-11-30 16:45:29 +0100 |
| commit | f796c6e0ec6769873d63b6fcfc64c0ac14ba3555 (patch) | |
| tree | 75ea5fdb98fd06d332549e55304295a21fee30ef | |
| parent | 51c67601f16899cac0b860b80b76ee674e135faa (diff) | |
| download | coreboot-f796c6e0ec6769873d63b6fcfc64c0ac14ba3555.tar.xz | |
driver/intel/fsp2_0: Add version parameter to FSP platform callback
Change-Id: Ibad1ad6bb9eedf2805981623e835db071d54c528
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/17497
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
| -rw-r--r-- | src/drivers/intel/fsp2_0/include/fsp/api.h | 2 | ||||
| -rw-r--r-- | src/drivers/intel/fsp2_0/memory_init.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/romstage.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/quark/romstage/fsp2_0.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/skylake/romstage/romstage_fsp20.c | 2 |
5 files changed, 5 insertions, 5 deletions
diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index b0120400c2..a8445ba708 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -41,7 +41,7 @@ void fsp_memory_init(bool s3wake); void fsp_silicon_init(bool s3wake); /* Callbacks for updating stage-specific parameters */ -void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd); +void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version); void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd); /* Callback after processing FSP notify */ diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index b83356163e..56de0ef6a4 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -316,7 +316,7 @@ static void do_fsp_memory_init(struct fsp_header *hdr, bool s3wake, die("FSPM_ARCH_UPD not found!\n"); /* Give SoC and mainboard a chance to update the UPD */ - platform_fsp_memory_init_params_cb(&fspm_upd); + platform_fsp_memory_init_params_cb(&fspm_upd, hdr->fsp_revision); /* Call FspMemoryInit */ fsp_raminit = (void *)(hdr->image_base + hdr->memory_init_entry_offset); diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index f1d4b57494..d623913086 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -237,7 +237,7 @@ static void fill_console_params(FSPM_UPD *mupd) } } -void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd) +void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { fill_console_params(mupd); mainboard_memory_init_params(mupd); diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c index d90bd38d85..17080a3baf 100644 --- a/src/soc/intel/quark/romstage/fsp2_0.c +++ b/src/soc/intel/quark/romstage/fsp2_0.c @@ -87,7 +87,7 @@ int fill_power_state(void) return ps->prev_sleep_state; } -void platform_fsp_memory_init_params_cb(FSPM_UPD *fspm_upd) +void platform_fsp_memory_init_params_cb(FSPM_UPD *fspm_upd, uint32_t version) { FSPM_ARCH_UPD *aupd; const struct device *dev; diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 8e083234a0..adb84423ac 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -132,7 +132,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg) m_cfg->PcieRpEnableMask = mask; } -void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd) +void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; FSP_M_TEST_CONFIG *m_t_cfg = &mupd->FspmTestConfig; |